Fast Models Reference Manual - ARM Information Center

Processor Components
4.2.8 Performance
The ARMCortexA15xnCT component provides high performance in all areas except VFP and
NEON instruction set execution which currently does not use code translation technology.
4.2.9 Library dependencies
The ARMCortexA15xnCT component has no dependencies on external libraries.
4.2.10 Differences between the CT model and RTL Implementations
The ARMCortexA15xnCT component differs from the corresponding revision of the ARM
Cortex-A15 RTL implementation in the following ways:
• The ARMCortexA15xnCT does not implement address filtering within the SCU. The
enable bit for this feature is ignored.
• The GIC does not respect the CFGSDISABLE signal. This leads to some registers being
accessible when they should not be.
• The Broadcast Translation Lookaside Buffer (TLB) or cache operations in the
ARMCortexA15xnCT model do not cause other processors in the cluster which are asleep
due to Wait For Interrupt (WFI) to wake up.
• The RR bit in the SCTLR is ignored.
• The Power Control Register in the system control coprocessor is implemented but writing
to it does not change the behavior of the model.
• When modeling the SCU, coherency operations are represented by a memory write
followed by a read to refill from memory, rather than using cache-to-cache transfers.
• ETM registers are not implemented.
• Debug-related components are not implemented. Processor debug registers and system
debug registers are not implemented.
• TLB bitmap registers are implemented as RAZ/WI.
• The Cortex-A15 mechanism to read the internal memory used by the Cache and TLB
structures through the implementation defined region of the system coprocessor interface
is not supported. This includes the RAM Index Register, IL1DATA Registers, DL1DATA
Registers, and associated functionality.
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