Fast Models Reference Manual - ARM Information Center

Accuracy and Functionality
Fast Models with cache-state modelling enabled can replicate all of these failure-cases.
However, they do not attempt to reproduce the following effects of caches:
• Changes to timing behavior of a program due to cache hits/misses (because the timing of
memory accesses is not modeled).
• Ordering of line-fill and eviction operations.
• Cache usage statistics (because the models do not generate accurate bus traffic).
• Device-accurate allocation of cache victim lines (which is not possible without accurate
bus traffic modelling).
• Write-streaming behavior where a cache spots patterns of writes to consecutive addresses
and automatically turns off the write-allocation policy.
Models with coherent L1 data-caches currently do not model device-accurate MESI behavior.
For example, cache-to-cache line transfers at L1 are handled in the model by flushing the data
to L2 and reading it back.
It is not currently possible to insert any devices between the processor and its L1 caches. In
particular, you can not model L1 traffic, although you can tell the model not to model the state
of L1 caches.
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