Fast Models Reference Manual - ARM Information Center

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Emulation Baseboard Model: Platform and Components 7.6 EBCortexA9_SysRegs component The EB Cortex-A9 system registers component is a programmer's view model of the Cortex-A9 specific status and system control registers. It overrides some of the system registers provided by the EB_SysRegs component. For a detailed description of the behavior of the component, refer to the hardware documentation. See the RealView Emulation Baseboard User Guide (Lead Free). Figure 7-4 on page 7-13 shows a view of the component in System Canvas. This component is written in LISA+. Figure 7-5 EBCortexA9_SysRegs in System Canvas 7.6.1 Ports Table 7-8 on page 7-13 provides a brief description of the EBCortexA9_SysRegs component ports. Refer to the hardware documentation for more details. Name Port Protocol Type Description Table 7-11 EBCortexA9_SysRegs ports reset_core[4] Signal master signals to reset separate processors reset_out Signal master reset signal sysreg_overrides EBSysRegs slave port to communicate with EB_SysRegs reset_in Signal slave reset signal 7.6.2 Additional protocols The EBCortexA9_SysRegs component has one additional protocol. The EBSysRegs protocol provides the rules to communicate with the EB_SysRegs component in order to override some of the system registers provided by the EB_SysRegs component. 7.6.3 Parameters The EBCortexA9_SysRegs component has no parameters. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-18 ID051811 Non-Confidential
Emulation Baseboard Model: Platform and Components 7.6.4 Registers Table 7-10 on page 7-15 provides a description of the configuration registers for the EBCortexA9_SysRegs component. Table 7-12 EBCortexA9_SysRegs registers Register name Offset Access Description SYS_RESETCTL 0x40 read/write Controls the software reset level SYS_PLDCTL1 0x74 read only Configure the attached core tiles SYS_PLDCTL2 0x78 read/write Configure the attached core tiles 7.6.5 Debug Features The EBCortexA9_SysRegs component has no debug features. 7.6.6 Verification and testing The EBCortexA9_SysRegs component has been tested as part of the Emulation Board model. 7.6.7 Performance The EBCortexA9_SysRegs component is not expected to significantly affect the performance of a PV system. 7.6.8 Library dependencies The EBCortexA9_SysRegs component has no dependencies on external libraries. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-19 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components Table 4-13 ARM
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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