Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
• Lockdown format C supported, for data and instructions. Lockdown format C is also
known as way locking.
• Lockdown by line supported.
• Lockdown by master id supported.
• Direct mapped to 16-way associativity, depending on the configuration and the use of
lockdown registers. The associativity is configurable as 8 or 16.
• L2 cache available size can be 16KB to 8MB, depending on configuration and the use of
the lockdown registers.
• Fixed line length of 32 bytes (eight words or 256 bits).
• Supports all of the AXI cache modes:
— write-through and write-back.
— read allocate, write allocate, read and write allocate.
• Force write allocate option to always have cacheable writes allocated to L2 cache, for
processors not supporting this mode.
• Normal memory non-cacheable shared reads are treated as cacheable non-allocatable.
Normal memory non-cacheable shared writes are treated as cacheable write-through no
write-allocate. There is an option, Shared Override, to override this behavior.
• TrustZone support, with the following features:
— Non-Secure (NS) tag bit added in tag RAM and used for lookup in the same way as
an address bit.
— NS bit in Tag RAM used to determine security level of evictions to L3.
— Restrictions for NS accesses for control, configuration, and maintenance registers
to restrict access to secure data.
• Pseudo-Random victim selection policy. You can make this deterministic with use of
lockdown registers.
• Software option to enable exclusive cache configuration.
• Configuration registers accessible using address decoding in the component.
• Interrupt triggering in case of an error response when accessing L3.
• Maintenance operations.
• Prefetching capability.
Hardware features not implemented
The following features of the PL310 hardware are not implemented in the PL310 model, most
of them are not relevant from a PV modelling point of view:
• There is no interface to the data and tag RAM as they are embedded to the model.
• Critical word first linefill not supported, as this is not relevant for PV modelling.
• Buffers are not modeled.
• Outstanding accesses on slave and master ports cannot occur by design in a PV model as
all transactions are atomic.
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