Fast Models Reference Manual - ARM Information Center

Processor Components
4.17 Implementation differences
This section outlines the differences between the code translation model implementations and
the actual hardware. It contains the following sections:
• Caches
• CP14 Debug coprocessor on page 4-89
• MicroTLB on page 4-89
• TLB on page 4-89
• Memory Access on page 4-90
• Timing on page 4-91
• VIC Port on page 4-91.
4.17.1 Caches
ARMv7 processor PV models, such as the Cortex-A9, Cortex-A8, and Cortex-R4, have
PV-accurate cache implementation. This means that the cache implementation is sufficient to
provide a functionally-accurate model. See the relevant processor component descriptions to
find out what specific features are implemented.
All other PV models do not model Level 1 or Level 2 caches. The system coprocessor registers
related to cache operations are modeled to allow cache aware software to work, but in most
cases they perform no operation other than to check register access permissions.
The registers affected on all code translation processor models are:
• Invalidate and/or Clean Entire ICache/DCache
• Invalidate and/or Clean ICache/DCache by MVA
• Invalidate and/or Clean ICache/DCache by Index
• Invalidate and/or Clean Both Caches
• Cache Dirty Status
• Data Write Barrier
• Data Memory Barrier
• Prefetch ICache Line
• ICache/DCache lockdown
• ICache/DCache master valid.
Additional registers affected on the ARMCortexA8CT model are:
• Preload Engine registers
• Level 1 System array debug registers
• Level 2 System array debug registers
• Level 2 Cache Lockdown
• Level 2 Cache Auxiliary control.
Additional registers affected on the ARMCortexR4CT model are:
• Cache Size Override
• Validation registers.
One additional register is affected on the ARM1176CT model:
• Cache behavior override.
Additional registers affected on the ARM1136CT model are:
• Read Block Transfer Status Register
• Stop Prefetch Range
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