Fast Models Reference Manual - ARM Information Center

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AEM ARMv7-A specifics A.2.3 Debug registers Access to architectural debug features is available through the debug registers. The AEM supports software access to the registers by three interfaces: • baseline CP14 interface • extended CP14 interface • memory-mapped interface. The registers can also be accessed through an external bus interface. This interface is implemented as a pvbus type slave port. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. A-9 ID051811 Non-Confidential
AEM ARMv7-A specifics A.3 IMPLEMENTATION DEFINED features Some aspects of the behavior of the processor are IMPLEMENTATION DEFINED in the ARM architecture, meaning that they can legally vary between different CPU implementations. Any code that is intended to be run portably across the multiple ARM implementations must take care when using any of these facilities, since they might or might not be present. The AEM uses some of these features differently to existing implementations. A.3.1 ACTLR The Auxiliary Control Register (ACTLR) is an IMPLEMENTATION DEFINED register that usually contains control bits to enable or disable certain processor-specific features. It is normally written very early in the bootstrap sequence, and is often not changed afterwards. In the AEM, the ACTLR has no functional bits implemented. Any changes to the configuration of the CPU must instead be carried out using the parameters in the CADI interface of the model. A.3.2 TLB lockdown The ARM architecture defines the concept of TLB lockdown but does not specify the register format used in its implementation. Code that runs portably across ARMv7-A implementations cannot use TLB lockdown except by selecting processor-specific code segments. The model supports TLB lockdown using the register scheme of the Cortex-A8, only if the size of the TLB is compatible with that format, that is, the TLB contains 32 entries or fewer. TLB lockdown is not available in cases where aggressive TLB pre-fetch is enabled. A.3.3 Internal peripherals Some ARM processors implement a set of internal peripheral components that are addressed by a range of programmer-visible physical addresses. The content and behavior of these peripherals are IMPLEMENTATION DEFINED. In default configuration, the AEM implements the set of peripherals defined in Table A-2. These are similar to the devices described in the Cortex-A9 MPCore Technical Reference Manual. The physical address of the peripherals is given as a fixed offset from the base address. The base address in the VE platform is 0x2C000000. When using the AEM as a component in other platforms, you can configure the base address with the PERIPHBASE parameter. Each component can also contain one or more interrupt sources, which are connected to the internal Generic Interrupt Controller (GIC) at the ID numbers specified. Table A-2 Internal peripherals Peripheral Address range Interrupt SCU 0x0000 - 0x00FF GIC 0x0100 - 0x01FF Legacy IRQ - 31 Legacy FIQ - 28 Global Timer 0x0200 - 0x02FF 27 Local Timer and Watchdog 0x0600 - 0x06FF Watchdog - 30 Local Timer - 29 Interrupt Distributer 0x1000 - 0x1FFF ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. A-10 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Page 311 and 312: Versatile Express Model: Platform a
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Page 359 and 360: AEM ARMv7-A specifics When stepping
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Page 367 and 368: Glossary DSR DTR EB GIC GPIO I/O KM
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