Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Bus master component
Slave device
PVBusMaster
subcomponent
PVBusSlave
subcomponent
PVBusDecoder
Other masters
Other slaves and
PVBusDecoders
Figure 5-1 Sample bus topology
All communication over the PVBus is performed using transactions that are generated by
PVBusMaster subcomponents and fulfilled by PVBusSlave components. Transactions can be
routed to the slave device through its PVBusSlave subcomponent. Once configured, the
PVBusSlave can handle memory-like transactions efficiently without needing to route these
transactions to the slave device. All transactions are atomic and untimed, in keeping with the
programmer's view abstraction.
PVBus examples
This document contains some examples of PVBus components in use. Additional examples can
be found in Fast Models. Paths to these examples are provided in Table 5-1. For paths on Linux,
substitute $PVLIB_HOME for the Microsoft Windows environment variable %PVLIB_HOME%.
Table 5-1 PVBus examples
Path
%PVLIB_HOME%\examples\Common\LISA\CPTimer.lisa
%PVLIB_HOME%\LISA\CounterModule.lisa
%PVLIB_HOME\examples\BusComponents\
%PVLIB_HOME%\examples\RTSM_VE\LISA\RTSMVersatileEB_1176.lisa
%PVLIB_HOME%\examples\Common\LISA\RemapDecoder.lisa
Description
A full implementation of a bus slave
device (CounterTimer module).
Copies of the examples in this user
guide.
Example of moderately complex
bus topology, using the
PVBusDecoder component.
An example that dynamically
modifies routing of requests based
on a remap signal, using the
TZSwitch component.
5.2.2 PVBusDecoder component
The PVBusDecoder provides support for mapping slave devices to different address ranges on
a bus. Incoming bus requests are routed to the appropriate slave device, based on the transaction
address.
Figure 5-2 on page 5-5 shows a view of the component in System Canvas.
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