Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Bank 2 register Table 5-122 lists the SMSC_91C111 bank 2 registers. Table 5-122 SMSC_91C111 bank 2 registers Register name Offset Access Description MMU_COMMAND 0x0 read/write MMU commands PNR 0x2 read/write Packet number ALLOCATED 0x3 read/write Allocated packet number FIFO_PORTS 0x4 read/write Tx/Rx FIFO packet number POINTER 0x6 read/write Address to access in Tx/Rx packet DATA 0x8 read/write Data register a INTERRUPT 0xC read/write Interrupt status INTERRUPT_MASK 0xD read/write Interrupt mask BANK 0xE read/write Bank select a. The data register can be accessed as 8, 16 or 32 bits and adjusts the pointer accordingly. Bank 3 register Table 5-123 lists the SMSC_91C111 bank 3 registers. Table 5-123 SMSC_91C111 bank 3 registers Register name Offset Access Description MT0_1 0x0 read/write Multicast table 0, 1 MT2_3 0x2 read/write Multicast table 2, 3 MT4_5 0x4 read/write Multicast table 4, 5 MT6_7 0x6 read/write Multicast table 6, 7 MGMT 0x8 read/write Management interface REVISION 0xA read only Chip revision ID ERCV 0xC read/write Early receive BANK 0xE read/write Bank select Debug features The SMSC_91C111 component has no debug features. Verification and testing The SMSC_91C111 component has been tested as part of the VE example system using VE test suites and by booting operating systems. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-145 ID051811 Non-Confidential
Peripheral and Interface Components Performance The SMSC_91C111 component is not expected to significantly affect the performance of a PV system. Library dependencies The SMSC_91C111 component has no dependencies on external libraries. 5.4.44 HostBridge component The HostBridge component is a virtual programmer’s view model. It acts as a networking gateway to exchange Ethernet packets with the TAP device on the host, and to forward packets to NIC models. This component is written in LISA+. Figure 5-64 HostBridge in System Canvas Ports Table 5-124 provides a brief description of the HostBridge component ports. Refer to the hardware documentation for more details. Name Port Protocol Type Description Table 5-124 HostBridge ports eth VirtualEthernet master Send or receive Ethernet frame. Additional protocols The HostBridge component has one additional protocol, VirtualEthernet. See VirtualEthernetCrossover on page 5-147. Parameters Table 5-125 provides a description of the configuration parameters for the HostBridge component. Table 5-125 HostBridge configuration parameters Parameter name Description Type Allowed value Default value interfaceName Host Interface string Valid string characters ARM0 Registers The HostBridge component has no registers. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-146 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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