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Fast Models Reference Manual - ARM Information Center

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Emulation Baseboard Model: Platform and Components<br />

Table 7-10 EB_SysRegs registers (continued)<br />

Register name Offset Access Description<br />

SYS_DMAPSR0 0x64 read/write DMA peripheral map<br />

SYS_DMAPSR1 0x68 read/write DMA peripheral map<br />

SYS_DMAPSR2 0x6C read/write DMA peripheral map<br />

SYS_IOSEL 0x70 read/write peripheral I/O select<br />

SYS_PLDCTL1 0x74 read/write configure the attached core<br />

tiles<br />

SYS_PLDCTL2 0x78 read/write configure the attached core<br />

tiles<br />

SYS_BUSID 0x80 read only bus ID<br />

SYS_PROCID0 0x84 read only processor ID<br />

SYS_PROCID1 0x88 read only processor ID<br />

SYS_OSCRESET0 0x8C read/write oscillator reset<br />

SYS_OSCRESET1 0x90 read/write oscillator reset<br />

SYS_OSCRESET2 0x94 read/write oscillator reset<br />

SYS_OSCRESET3 0x98 read/write oscillator reset<br />

SYS_OSCRESET4 0x9C read/write oscillator reset<br />

SYS_VOLTAGE0 0xA0 read/write core tile configuration<br />

SYS_VOLTAGE1 0xA4 read/write core tile configuration<br />

SYS_VOLTAGE2 0xA8 read/write core tile configuration<br />

SYS_VOLTAGE3 0xAC read/write core tile configuration<br />

SYS_VOLTAGE4 0xB0 read/write core tile configuration<br />

SYS_VOLTAGE5 0xB4 read/write core tile configuration<br />

SYS_VOLTAGE6 0xB8 read/write core tile configuration<br />

SYS_VOLTAGE7 0xBC read/write core tile configuration<br />

SYS_TEST_OSC0 0xC0 read only oscillator test<br />

SYS_TEST_OSC1 0xC4 read only oscillator test<br />

SYS_TEST_OSC2 0xC8 read only oscillator test<br />

SYS_TEST_OSC3 0xCC read only oscillator test<br />

SYS_TEST_OSC4 0xD0 read only oscillator test<br />

SYS_T1_PLD_DATA 0xE0 read/write PLD configuration<br />

SYS_T2_PLD_DATA 0xE4 read/write PLD configuration<br />

SYS_GPIO 0xE8 read/write GPIO<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 7-16<br />

ID051811<br />

Non-Confidential

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