Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Registers
Table 5-51 provides a description of the configuration registers for the PL061_GPIO
component.
Table 5-51 PL061_GPIO registers
Register
name
Offset Access Description
GPIODATA 0x000 -
0x3FC
read/write
GPIO prime data register.
The address offsets serve as
a mask. Only bits [11:2] are
valid as the mask. a
GPIODIR 0x400 read/write Data direction register. Set
for output, clear for input.
GPIOIS 0x404 read/write Interrupt sense register. Set
for level trigger, clear for
edge trigger.
GPIOIBE 0x408 read/write Bits set, both edges on
corresponding pin trigger
and interrupt.
GPIOIEV 0x40C read/write Interrupt event register. Bit
set for rising edge or high
level trigger.
GPIOIE 0x410 read/write Interrupt mask register.
GPIORIS 0x414 read Raw interrupt status
register.
GPIOMIS 0x418 read Masked interrupt status
register.
GPIOIC 0x41C write Interrupt clear register.
GPIOAFSEL 0x420 read/write Mode control select
GPIOPeriphID0 0xfe0 read Peripheral ID register
GPIOPeriphID1 0xfe4 read Peripheral ID register
GPIOPeriphID2 0xfe8 read Peripheral ID register
GPIOPeriphID3 0xfec read Peripheral ID register
GPIOPCellID0 0xff0 read PrimeCell ID register
GPIOPCellID1 0xff4 read PrimeCell ID register
GPIOPCellID2 0xff8 read PrimeCell ID register
GPIOPCellID3 0xffc read PrimeCell ID register
a. For writes, values written to the registers are transferred onto the GPOIT pins
if the respective pins have been configured as output ports. Set certain pins in
GPIO_Mask to high to enable writing. A similar process applies to reads.
Details of how to use this register are covered elsewhere. See the ARM
PrimeCell General Purpose Input/Output (PL061) Technical Reference
Manual.
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