Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Registers
Table 5-60 provides a description of the configuration registers for the PL111_CLCD
component.
Table 5-60 PL111_CLCD registers
Register name Offset Access Description
LCDTiming0 0x0 read/write Horizontal timing
LCDTiming1 0x4 read/write Vertical timing
LCDTiming2 0x8 read/write Clock and polarity control
LCDTiming3 0xC read/write Line end control
LCDUPBASE 0x10 read/write Upper panel frame base
address
LCDLPBASE 0x14 read/write Lower panel frame base
address
LCDControl 0x18 read/write Control
LCDIMSC 0x1C read/write Interrupt mask
LCDRIS 0x20 read only Raw interrupt status
LCDMIS 0x24 read only Masked interrupt status
LCDICR 0x28 write only Interrupt clear
LCDIPCURR 0x2C read only Upper panel current address
LCDLPCURR 0x30 read only Lower panel current address
LCDPalette 0x200 -
0x3FC
read/write
Palette registers
CursorImage 0x800-0xBFC read/write Cursor image RAM register
ClcdCrsCtrl 0xC00 read/write Cursor control
ClcdCrsrConfig 0xC04 read/write Cursor configuration
ClcdCrsrPalette0 0xC08 read/write Cursor palette
ClcdCrsrPalette1 0xC0C read/write Cursor palette
ClcdCrsrXY 0XC10 read/write Cursor XY position
ClcdCrsrClip 0xC14 read/write Cursor clip position
ClcdCrsrIMSC 0xc20 read/write Cursor interrupt mask
set/clear
ClcdCrsrICR 0xc24 read/write Cursor interrupt clear
ClcdCrsrRIS 0xc28 read/write Cursor raw interrupt status
ClcdCrsrMIS 0xc2c read/write Cursor masked interrupt
status
CLCDPeriphID0 0xfe0 read Peripheral ID register
CLCDPeriphID1 0xfe4 read Peripheral ID register
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