Fast Models Reference Manual - ARM Information Center

Processor Components
4.7 ARMCortexA5CT
Figure 4-6 shows a view of the ARMCortexA5CT component in System Canvas. This is a
model of the Cortex-A5 uniprocessor, which is a single processor. The component is based on
r0p0 of the Cortex-A5 processor.
This component is written in C++.
Figure 4-6 ARMCortexA5CT in System Canvas
4.7.1 Ports
Table 4-15 provides a brief description of the ports in the ARMCortexA5CT component. Refer
to the processor technical reference manual for more details.
Name Port protocol Type Description
Table 4-15 ARMCortexA5CT ports
cfgend[0] Signal slave Initialize to BE8 endianness after a reset.
cfgnmfi[0] Signal slave Enable non-maskable fast interrupts after a reset.
clk_in ClockSignal slave Main CPU clock input.
clusterid Value slave Value read in MPIDR register.
cp15sdisable[0] Signal slave Disable write access to some cp15 registers.
event Signal peer Event input and output for wakeup from WFE. This port
amalgamates the EVENTI and EVENT0 signals that are
present on hardware.
fiq[0] Signal slave Processor FIQ signal input.
irq[0] Signal slave Processor IRQ signal input.
pmuirq[0] Signal master Performance Monitoring Unit (PMU) interrupt signal.
pvbus_m0 PVBus master AXI master 0 bus master channel.
reset[0] Signal slave Processor reset signal.
standbywfe[0] Signal master Indicates if a processor is in WFE state.
standbywfi[0] Signal master Indicates if a processor is in WFI state.
teinit[0] Signal slave Initialize to take exceptions in Thumb state after a reset.
ticks[0] InstructionCount master Processor instruction count for visualization.
vinithi[0] Signal slave Initialize with high vectors enabled after a reset.
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