Fast Models Reference Manual - ARM Information Center

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Emulation Baseboard Model: Platform and Components On reset, the EB hardware starts to execute code at 0x0, which is typically volatile DRAM. You can put the contents of non-volatile RAM at this location by setting the S8 switch in the EB RTSM CLCD as shown in Table 7-5. The settings take effect on model reset. Table 7-5 EB System Model switch S8 settings Switch S8[4:1] Memory Range Description 0000 0x40000000–0x4FEFFFFF NOR flash remapped to 0x0 0001 0x44000000–0x47FFFFFF NOR flash remapped to 0x0 0010 0x48000000–0x4BFFFFFF SRAM remapped to 0x0 Note Attempting to change switch S8 settings after the model has started, for example by using the CLCD DIP switches, might lead to unpredictable behavior. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-8 ID051811 Non-Confidential
Emulation Baseboard Model: Platform and Components 7.4 EBVisualisation component The EBVisualisation component can generate events when the host mouse or keyboard are used when the visualization window is in focus. For example, the switch elements can be toggled from the visualization window. Figure 7-1 shows the startup CLCD visualization window for the EB RTSM. Figure 7-1 EB Real-Time System Model CLCD visualization window When a suitable application or system image is loaded, and has configured the PL110_CLCD controller registers, the window expands to show the contents of the frame buffer. Figure 7-2 shows an example using the brot.axf image. Figure 7-2 EB RTSM CLCD with brot.axf image Further details on how to use the features provided in the CLCD visualization window are given elsewhere. See the RealView Development Suite Real-Time System Models User Guide. Figure 7-3 on page 7-10 shows a view of the EBVisualisation component in System Canvas. This component can be found in the %PVLIB_HOME%\examples\RTSM_EB\LISA\ directory. On Linux, use the $PVLIB_HOME/examples/RTSM_EB/LISA directory. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-9 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Fast Models Reference Manual - ARM Information Center

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