Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Ports
Table 5-66 provides a brief description of the PL192_VIC component ports. Refer to the
component documentation for more details.
Name Port protocol Type Description
Table 5-66 PL192_VIC ports
VICIntSource [32] Signal Slave Interrupt source input sources
VICVECTADDRIN Value Slave Used to receive vector address when
daisy chained
nVICFIQIN Signal Slave Used to receive FIQ signal when daisy
chained
nVICIRQIN Signal Slave Used to receive IRQ signal when daisy
chained
pvbus PVBus Slave Slave port for connection to PV bus
master/decoder
VICIRQACK Signal Slave Receive acknowledge signal from next
level VIC or CPU
VICIRQACKOUT Signal Master Used to send out acknowledge signals
when daisy chained
VICVECTADDROUT Value Master Used to send vector address to next level
VIC or CPU
nVICFIQ Signal Master Send out FIQ signal to the next level
VIC or CPI
nVICIRQ Signal Master Send out IRQ signal to the next level
VIC or CPU
Additional protocols
The PL192_VIC component has no additional protocols.
Parameters
The PL192_VIC component has no parameters.
Registers
Table 5-67 provides a description of the configuration registers for the PL192_VIC component.
Table 5-67 PL192_VIC registers
Register name Offset Access Description
IRQSTATUS 0x000 read only IRQ status register
FIQSTATUS 0x004 read only FIQ status register
RAWINTR 0x008 read only Raw interrupt status register
INTSELECT 0x00C read/write Interrupt select register
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