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Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components<br />

Debug features<br />

The PL061_GPIO component has no debug features.<br />

Verification and testing<br />

The functions of the PL061_GPIO component have been tested individually using a tailored test<br />

suite.<br />

Performance<br />

The PL061_GPIO component is not expected to significantly affect the performance of a PV<br />

system.<br />

Library dependencies<br />

The PL061_GPIO component has no dependencies on external libraries.<br />

5.4.15 PL080_DMAC component<br />

The PL080_DMAC component is a programmer's view model of the <strong>ARM</strong> PL080 DMA<br />

Controller. It provides eight configurable DMA channels, and 16 DMA ports for handshaking<br />

with peripherals. You can configure each channel to operate in one of eight flow control modes<br />

either under DMA control or the control of the source or destination peripheral. Transfers can<br />

occur on either master channel and can optionally be endian converted on both source and<br />

destination transfers. Refer to external documentation for additional details on the PL080. See<br />

the <strong>ARM</strong> PrimeCell DMA Controller (PL080) Technical <strong>Reference</strong> <strong>Manual</strong>.<br />

Figure 5-34 shows a view of the component in System Canvas.<br />

This component is written in LISA+.<br />

Figure 5-34 PL080_DMAC in System Canvas<br />

Ports<br />

Table 5-52 provides a brief description of the ports in the PL080_DMAC component. Refer to<br />

the component documentation for more details.<br />

Name Port protocol Type Description<br />

Table 5-52 PL080_DMAC ports<br />

pvbus_s PVBus Slave Slave bus for register accesses<br />

clk_in ClockSignal Slave Clock signal to control DMA transfer<br />

rate<br />

reset_in Signal Slave Reset signal<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 5-66<br />

ID051811<br />

Non-Confidential

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