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Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components<br />

PVDevice protocol<br />

The PVDevice protocol enables you to implement support for memory-mapped device registers.<br />

The two methods are called through the device port on the PVBusSlave, in order to handle bus<br />

read/write transactions:<br />

read(pv::ReadTransaction) : pv::Tx_Result<br />

This method allows a device to handle a bus read transaction.<br />

write(pv::WriteTransaction) : pv::Tx_Result<br />

This method allows a device to handle a bus write transaction.<br />

The C++ transaction and Tx_Result classes are described in further detail. See C++ classes on<br />

page 5-15.<br />

The PVDevice protocol uses two optional behaviors to differentiate between transaction<br />

originating from the CPU (loads and stores) and transactions originating from an attached<br />

debugger:<br />

optional slave behavior debugRead(pv::ReadTransaction tx) : pv::Tx_Result<br />

If implemented, this method enables the device to handle a debug read<br />

transaction.<br />

optional slave behavior debugWrite(pv::WriteTransaction tx) : pv::Tx_Result<br />

If implemented, this method enables the device to handle a debug write<br />

transaction.<br />

If the debugRead and debugWrite behaviors are implemented, they are called for all debug<br />

transactions. If they are not implemented, debug transactions are handled by the read and write<br />

behaviors.<br />

PVBusSlaveControl<br />

setFillPattern(uint32_t fill1, uint32_t fill2)<br />

This sets a two-word alternating fill pattern to be used by uninitialized memory.<br />

setAccess(pv::bus_addr_t base, pv::bus_addr_t top, pv::accessType type, pv::accessMode<br />

mode)<br />

This reconfigures handling for a region of memory.<br />

base (inclusive value) and top (exclusive value) specify the address range to<br />

configure. Both base and top values must be 4KB page aligned.<br />

type selects what types of bus access must be reconfigured. It can be one of:<br />

• pv::ACCESSTYPE_READ<br />

• pv::ACCESSTYPE_WRITE<br />

• pv::ACCESSTYPE_RW<br />

mode defines how bus accesses must be handled. See pv::accessMode values on<br />

page 5-11.<br />

*getReadStorage(pv::bus_addr_t address, pv::bus_addr_t *limit) : const uint8_t*<br />

*getWriteStorage(pv::bus_addr_t address, pv::bus_addr_t *limit) : uint8_t *<br />

These two methods allow you to access the underlying storage that PVBusSlave<br />

allocates to implement a region of memory.<br />

The return value is a pointer to the byte that represents the storage corresponding<br />

to the address of base.<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 5-10<br />

ID051811<br />

Non-Confidential

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