Fast Models Reference Manual - ARM Information Center

More documents

Recommendations

Info

AEM ARMv7-A specifics use_Cortex-A15_peripherals mode When the parameter use_Cortex-A15_peripherals is set to true, the AEM implements the set of peripherals defined in Table A-3. These are similar to the devices described in the Cortex-A15 Technical Reference Manual. Table A-3 Internal peripherals (use_Cortex-A15_peripherals) Peripheral Reserved Interrupt Controller Distributer Interrupt Controller Physical CPU Interface Interrupt Controller Virtual CPU Interface (Hypervisor view for requesting CPU) Interrupt Controller Virtual CPU Interface (Hypervisor view for all CPUs) Interrupt Controller Virtual CPU Interface (Virtual Machine view) Address range 0x0000 - 0x0FFF 0x1000 - 0x1FFF 0x2000 - 0x3FFF 0x4000 - 0x4FFF 0x5000 - 0x5FFF 0x6000 - 0x7FFF The interrupt controller is a Virtual Generic Interrupt Controller (VGIC). Note The generic timer becomes available by CP15 system control operations. For more information, see https://esl-support.arm.com/ ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. A-11 ID051811 Non-Confidential
AEM ARMv7-A specifics A.4 Trace The AEM includes support for Model Trace Interface (MTI) trace plug-ins. This enables the generation of trace files that track the execution of instructions, memory accesses, and other related operations of the CPU. For more information about this interface and the usage of trace plug-ins, see the Fast Models Tarmac Trace User Guide. A.4.1 TarmacTraceAEM The AEM model includes a trace plug-in with some enhanced capabilities, in addition to those described in the Fast Models Tarmac Trace User Guide. It is loaded when specified by a command-line option to Model Debugger: --trace-plugin /lib/TarmacTraceAEM.dll Additional capabilities are enabled using the parameters listed in trace_mmu, which become available in the trace parameters hierarchy. trace_mmu Lines prefixed TTW describe the data that has been read by a translation table walk. The line specifies the address from which the descriptor is read, the data returned from that address, and a summary of how that data is interpreted. Lines prefixed TLB describe a translation entry that has been added to the TLB. The line specifies whether the d-side or i-side TLB is being loaded, the size of the entry, and the mapping from VA to PA. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. A-12 ID051811 Non-Confidential
Page 1 and 2:
Fast Models Version 6.1 Reference M
Page 3 and 4:
Contents Fast Models Reference Manu
Page 5 and 6:
Preface This preface introduces the
Page 7 and 8:
Preface Typographical conventions T
Page 9 and 10:
Preface Feedback ARM welcomes feedb
Page 11 and 12:
Introduction 1.1 About the componen
Page 13 and 14:
Accuracy and Functionality 2.1 Mode
Page 15 and 16:
Accuracy and Functionality 2.2.2 Pe
Page 17 and 18:
Accuracy and Functionality 2. For a
Page 19 and 20:
Accuracy and Functionality Fast Mod
Page 21 and 22:
Signaling and Clocking Protocols 3.
Page 23 and 24:
Signaling and Clocking Protocols 3.
Page 25 and 26:
Signaling and Clocking Protocols Pa
Page 27 and 28:
Signaling and Clocking Protocols Ve
Page 29 and 30:
Chapter 4 Processor Components This
Page 31 and 32:
Processor Components 4.2 ARMCortexA
Page 33 and 34:
Processor Components InstructionCou
Page 35 and 36:
Processor Components c. This is a m
Page 37 and 38:
Page 39 and 40:
Processor Components Table 4-4 ARMC
Page 41 and 42:
Page 43 and 44:
Processor Components 4.3.9 Library
Page 45 and 46:
Page 47 and 48:
Processor Components a. The ase-pre
Page 49 and 50:
Processor Components 4.4.8 Performa
Page 51 and 52:
Processor Components 4.5.3 Paramete
Page 53 and 54:
Processor Components The debugger m
Page 55 and 56:
Processor Components 4.6.1 Ports Ta
Page 57 and 58:
Processor Components Table 4-13 ARM
Page 59 and 60:
Processor Components 4.6.5 Caches T
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
Processor Components 4.7.8 Performa
Page 67 and 68:
Processor Components Name Port Prot
Page 69 and 70:
Page 71 and 72:
Processor Components b. Currently i
Page 73 and 74:
Processor Components 4.9 ARMCortexR
Page 75 and 76:
Page 77 and 78:
Processor Components 4.9.9 Library
Page 79 and 80:
Processor Components Name Port prot
Page 81 and 82:
Processor Components The debugger m
Page 83 and 84:
Processor Components 4.11 ARMCortex
Page 85 and 86:
Page 87 and 88:
Processor Components 4.12 ARMv7A -
Page 89 and 90:
Processor Components pwrctli[0-3] V
Page 91 and 92:
Processor Components Table 4-29 Pro
Page 93 and 94:
Processor Components Cache geometry
Page 95 and 96:
Processor Components Note In the vi
Page 97 and 98:
Processor Components Message config
Page 99 and 100:
Processor Components All entries in
Page 101 and 102:
Processor Components 4.13.3 Paramet
Page 103 and 104:
Processor Components Memory The ARM
Page 105 and 106:
Page 107 and 108:
Processor Components Memory The ARM
Page 109 and 110:
Page 111 and 112:
Processor Components 4.15.5 Debug f
Page 113 and 114:
Processor Components 4.16 ARM926CT
Page 115 and 116:
Processor Components Registers All
Page 117 and 118:
Processor Components • Data/Instr
Page 119 and 120:
Processor Components DMA DMA is cur
Page 121 and 122:
Processor Components Table 4-47 Cor
Page 123 and 124:
Peripheral and Interface Components
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Versatile Express Model: Platform a
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314: Chapter 7 Emulation Baseboard Model
Page 315 and 316: Emulation Baseboard Model: Platform
Page 339 and 340: Microcontroller Prototyping System:
Page 355 and 356: AEM ARMv7-A specifics A.1 Boundary
Page 357 and 358: AEM ARMv7-A specifics When paramete
Page 359 and 360: AEM ARMv7-A specifics When stepping
Page 361 and 362: AEM ARMv7-A specifics A.2 Debug arc
Page 363: AEM ARMv7-A specifics A.3 IMPLEMENT
Page 367 and 368: Glossary DSR DTR EB GIC GPIO I/O KM
show all

Fast Models Reference Manual - ARM Information Center

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?