Fast Models Reference Manual - ARM Information Center

AEM ARMv7-A specifics
AP==110 deprecated
Pagetable entries using the encoding AP[2] = 1, AP[1:0] = 0b10 means read-only for both
privileged mode and user mode accesses, but its use is deprecated in VMSAv7. Instead use AP[2]
= 1, AP[1:0] = 0b11.
A dirty cache line was invalidated but not cleaned
When the invalidate cache maintenance operation is performed on a writeback cache, the data
in any dirty lines might or might not have been flushed to the next cache level or backing RAM.
Any subsequent data reads from that address are therefore ambiguous. It is legal to do this, but
take care that it is not used improperly or else bugs can be introduced.
Reserved encoding
When extended addressing is in use, each 8-bit field of the MAIR0 and MAIR1 registers must be
written with a valid memory type. Writing any field with values of the following form is
unpredictable:
• 0xyy xxxx for values of yy other than 0
• xxxx 0xyy for values of yy other than 0
• yyyy 0000 for values of yyyy other than 0
• 0000 1xxx.
Incoherency between S and NS memory
Some system platforms (such as the VE) do not distinguish between SECURE and
NON_SECURE memory accesses, and the storage destination depends only on the physical
address regardless of the NS bit. In these cases, using S and NS versions of the same physical
address can have unpredictable cache incoherency effects. For example, if the cache contains
dirty lines for the same address in each state, the final memory contents depend on random
eviction order.
When the AEM, however, is used as a component in a system platform that distinguishes
between S and NS accesses, this usage is perfectly legal and recommended, so this warning must
be disabled by decreasing the value of the messages.severity_level_E_ReservedEncoding
parameter.
Exception level change
Various unpredictable effects can occur if an MSR or CPS instruction is used to change privilege
level, for example, leaving monitor mode with SCR.NS==0, leaving hyp mode, or entering user
mode.
In preference, target code must use one of the exception return operations such as RFE, ERET or
SUBS PC, LR.
ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. A-7
ID051811
Non-Confidential