Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Performance
The PL340_DMC component has negligible impact on performance.
Library dependencies
The PL340_DMC component has no dependencies on external libraries.
5.4.23 PL350_SMC component
The PL350_SMC component is a programmer's view model of the ARM PL350 Static Memory
Controller (SMC). It provides two memory interfaces. Each interface can be connected to a
maximum of four memory devices, giving a total of eight inputs from the PVBusDecoder and
eight outputs to either SRAM or NAND devices. Only one kind of memory can be connected to
a particular interface, either SRAM or NAND. Further technical details on the SMC are
described elsewhere. See the ARM PrimeCell Static Memory Controller (PL350 series)
Technical Reference Manual.
The PL350_SMC component implementation provides a PVBus slave to control the device
behavior. A remap port is also provided to assist in remapping particular memory regions.
Figure 5-43 shows a view of the component in System Canvas.
This component is written in LISA+.
Figure 5-43 PL350_SMC in System Canvas
Ports
Table 5-74 provides a brief description of the ports for the PL350_SMC component. Refer to
the component documentation for more details. See ARM PrimeCell Static Memory Controller
(PL350 series) Technical Reference Manual.
Name Port protocol Type Description
Table 5-74 PL350_SMC ports
axi_chip_if0_in[4] PVBus Slave Slave bus for interface 0 connecting to
memory
axi_chip_if1_in[4] PVBus Slave Slave bus for interface 1 PVBus
connecting to memory
apb_interface PVBus Slave Slave bus interface for register access
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