Fast Models Reference Manual - ARM Information Center

Processor Components
4.9.4 Registers
The ARMCortexR4CT component provides the registers specified by the technical reference
manual for the Cortex-R4 with the following exceptions:
• coprocessor 14 registers are not implemented
• integration and test registers are not implemented.
4.9.5 Caches
The ARMCortexR4CT component implements a PV-accurate view of cache.
4.9.6 Debug features
The ARMCortexR4CT component exports a CADI debug interface.
Registers
All processor and CP15 registers are visible in the debugger. See the processor technical
reference manual for a detailed description of available registers.
The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register
has no defined behavior.
Breakpoints
There is direct support for:
• single address unconditional instruction breakpoints
• unconditional instruction address range breakpoints
• single address unconditional data breakpoints.
The debugger might augment these with more complex combinations of breakpoints.
The current models support processor exception breakpoints by pseudo-registers that are
available in the debugger register window. When debugger support is added to directly support
processor exceptions, the pseudo-registers are removed.
Setting an exception register to a non-zero value causes execution to stop on entry to the
associated exception vector.
Memory
The ARMCortexR4CT component presents one 4GB view of virtual memory.
4.9.7 Verification and testing
The ARMCortexR4CT component has been tested using:
• the architecture validation suite tests for the ARM Cortex-A4
• booting of ucLinux and ThreadX Symbian on an example system containing an
ARMCortexR4CT component.
4.9.8 Performance
The ARMCortexR4CT component provides high performance in all areas except with
instructions in protection regions smaller than 1KB, and VFP instruction set execution which
currently does not use code translation technology.
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