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Fast Models Reference Manual - ARM Information Center

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Processor Components<br />

4.6 <strong>ARM</strong>CortexA5MPxnCT<br />

Figure 4-5 shows a view of the <strong>ARM</strong>CortexA5MPxnCT component in <strong>Fast</strong> <strong>Models</strong>, with all<br />

vectored ports collapsed. This is a single component that represents a Cortex-A5 multiprocessor<br />

containing from one to four processors. The xn in the component name indicates how many<br />

processors are included in the component, so choose the one with the required number of<br />

processors for your system. The component is based on r0p0 of the Cortex-A5 processor. All<br />

variants of the <strong>ARM</strong>CortexA5MPxnCT component are described in this section, the only<br />

difference being the number of processors.<br />

The <strong>ARM</strong>CortexA5MPxnCT component implements the following additional peripherals, that<br />

are not present in the basic Cortex-A5 processor:<br />

• Snoop Control Unit (SCU)<br />

• Generic Interrupt Controller (GIC)<br />

• private timer and watchdog for each processor<br />

• global timer<br />

• Advanced Coherency Port (ACP)<br />

These embedded peripherals are more fully documented elsewhere. See the processor technical<br />

reference manual.<br />

This component is written in C++.<br />

Figure 4-5 <strong>ARM</strong>CortexA5MPCT in System Canvas 1<br />

1. Array ports have been collapsed in this diagram.<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 4-26<br />

ID051811<br />

Non-Confidential

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