Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
For data transfer in the controller to card direction, the behaviors are:
Tx
Tx_done
After the host and controller have initiated a write through the command
interface, the card calls the Tx behavior on the controller. The call provides a
pointer to an empty buffer to be written, and a length. The ARM MMC reference
model simulates device write latency by waiting a number of clock cycles prior
to each buffer being offered.
The controller calls this behavior on the card when the block has been written.
The card model can then commit the data to its persistent storage.
The card model must also implement:
cmd_name
This behavior returns the name of the command issued. A card must implement
this behavior, but is free to return an empty string for all requests. Only call this
behavior for diagnostic messages.
Parameters
The PL180_MCI component has no parameters.
Registers
Table 5-62 provides a description of the configuration registers for the PL180_MCI component.
Table 5-62 PL180_MCI registers
Register name Offset Access Description
MCIPower 0x000 read/write Power control register
MCIClock 0x004 read/write Clock control register
MCIArgument 0x008 read/write Argument register
MCICommand 0x00C read/write Command register
MCIRespCmd 0x010 read only Response command register
MCIResponse0 0x014 read only Response register
MCIResponse1 0x018 read only response registerR
MCIResponse2 0x01C read only Response register
MCIResponse3 0x020 read only Response register
MCIDataTimer 0x024 read/write Data timer
MCIDataLength 0x028 read/write Data length register
MCIDataCtrl 0x02C read/write Data control register
MCIDataCnt 0x030 read only Data counter
MCIStatus 0x034 read only Status register
MCIClear 0x038 write only Clear register
MCIMask0 0x03C read/write Interrupt 0 mask register
MCIMask1 0x040 read/write Interrupt 1 mask register
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