Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Table 5-67 PL192_VIC registers (continued)
Register name Offset Access Description
INTENABLE 0x010 read/write Interrupt enable register
INTENCLEAR 0x014 write only Interrupt enable clear
register
SOFTINT 0x018 read/write Software interrupt register
SOFTINTCLEAR 0x01C write only Software interrupt clear
register
PROTECTION 0x020 read/write Protection enable register
SWPRIORITY 0x024 read/write Software priority mask
PRIORITYDAISY 0x028 read/write Vector priority register for
daisy chain
VECTADDR[0:31] 0x100 -
0x17C
VECTPRIORITY[0:31] 0x200 -
0x27C
read/write
read/write
32 vector addresses
32 priority registers
VICADDRESS 0xF00 read/write Vector address register
Debug features
The PL192_VIC component has no debug features.
Verification and testing
The PL192_VIC has been run against the RTL validation suite and has been successfully used
in validation platforms.
Performance
The PL192_VIC component is not expected to significantly affect the performance of a PV
system.
Library dependencies
The PL192_VIC component has no dependencies on external libraries.
5.4.21 PL310_L2CC component
The PL310_L2CC provides a model of an Level 2 Cache Controller (L2CC). The presence of
additional on-chip secondary cache can improve performance when significant memory traffic
is generated by the processor. A secondary cache assumes the existence of a Level 1, or primary,
cache, which is closely coupled or internal to the processor. For more information, refer to the
component documentation. See the ARM PrimeCell Level 2 Cache Controller (PL310)
Technical Reference Manual. For more information about the accuracy and functionality of Fast
Models and cache models see Chapter 2 Accuracy and Functionality.
The PL310_L2CC component has two modes of operation
• Register view: Cache control registers are present but the cache behavior is not modeled.
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