Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Table 5-70 PL310_L2CC registers (continued) Register name Offset Access Description InterruptMask 0x214 read/write r2 interrupt mask MaskedInterruptStatus 0x218 read only r2 masked interrupt status RawInterruptStatus 0x21C read only r2 raw interrupt status InterruptClear 0x220 write only r2 interrupt clear CacheSync a 0x730 read/write r7 cache sync InvalidateByPA 0x770 read/write r7 invalidate line by PA InvalidateByWay 0x77C read/write r7 invalidate by way CleanByPA 0x7B0 read/write r7 clean line by PA CleanByIdxWay 0x7B8 read/write r7 clean line by index or way CleanByWay 0x7BC read/write r7 clean by way CleanInvalByPA 0x7F0 read/write r7 clean and invalidate line by PA CleanInvalByIdxWay 0x7F8 read/write r7 clean and invalidate line by index or way CleanInvalByWay 0x7FC read/write r7 clean and invalidate by way DataLockdown0 0x900 read/write r9 data lockdown 0 by way InstructionLockdown0 0x904 read/write r9 instruction lockdown 0 by way DataLockdown1 0x908 read/write r9 data lockdown 1 by way InstructionLockdown1 0x90C read/write r9 instruction lockdown 1 by way DataLockdown2 0x910 read/write r9 data lockdown 2 by way InstructionLockdown2 0x914 read/write r9 instruction lockdown 2 by way DataLockdown3 0x918 read/write r9 data lockdown 3 by way InstructionLockdown3 0x91C read/write r9 instruction lockdown 3 by way DataLockdown4 0x920 read/write r9 data lockdown 4 by way InstructionLockdown4 0x924 read/write r9 instruction lockdown 4 by way DataLockdown5 0x928 read/write r9 data lockdown 5 by way InstructionLockdown5 0x92C read/write r9 instruction lockdown 5 by way DataLockdown6 0x930 read/write r9 data lockdown 6 by way ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-89 ID051811 Non-Confidential
Peripheral and Interface Components InstructionLockdown6 0x934 read/write r9 instruction lockdown 6 by way DataLockdown7 0x938 read/write r9 data lockdown 7 by way InstructionLockdown7 0x93C read/write r9 instruction lockdown 7 by way LockdownByLineEnable 0x950 read/write r9 lockdown by line enable UnlockAll 0x954 read/write r9 unlock all lines by way AFilterStart a 0xC00 read/write r12 address filtering start AFilterEnd a 0xC04 read/write r12 address filtering end DebugControl a 0xF40 read/write r15 debug control register a. Operation of this register is not functionally modeled. Table 5-70 PL310_L2CC registers (continued) Register name Offset Access Description Debug features The PL310_L2CC component exports the PL310 registers by CADI. Verification and testing The PL310_L2CC has been run against the RTL validation suite and passes for supported features. It has also been tested with operating system booting in both normal and exclusive modes, and has successfully used in validation platforms. Performance The performance of the PL310_L2CC component depends on the configuration of the associated L1 caches and the mode it is in. • register mode: The PL310_L2CC model does not significantly affect performance. • functional mode with functional-mode L1: the addition of a functional L2 cache has minimal further impact on performance when running applications that are cache-bound. • functional mode with a register-mode L1: the PL310_L2CC has a significant impact on system performance in this case. Library dependencies The PL310_L2CC component has no dependencies on external libraries. Functionality The PL310 implements the programmer visible functionality of the PL310, and excludes some non-programmer visible features. Implemented hardware features The following features of the PL310 hardware are implemented in the PL310 model: • Physically addressed and physically tagged. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-90 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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