Fast Models Reference Manual - ARM Information Center

Processor Components
InstructionCount
The InstructionCount protocol has one behavior.
getValue
obtain the number of instructions executed by the processor.
4.2.3 Parameters
Table 4-2 provides a description of the configuration parameters for the ARMCortexA15xnCT
component. These parameters are set once, irrespective of the number of Cortex-A15 processors
in your system. If you have multiple Cortex-A15 processors, then each processor has its own
configuration parameters, as shown in Table 4-3 on page 4-6.
Table 4-2 ARMCortexA15xnCT parameters
Parameter Description Type
Allowed
Value
Default
Value
CFGSDISABLE Disable some accesses to DIC registers. boolean true or false false
CLUSTER_ID CPU cluster ID value. integer 0-15 0
device-accurate-tlb
Set whether device-accurate number of
TLBs are modeled
boolean true or false false a
dic-spi_count
Number of shared peripheral interrupts
implemented.
integer
0-224, in
increments of
32
64
IMINLN
l1_dcache-state_modelled
l1_icache-state_modelled
Instruction cache minimum line size:
false=32 bytes, true=64 bytes
Set whether L1 D-cache has stateful
implementation
Set whether L1 I-cache has stateful
implementation
boolean true or false true
boolean true or false false
boolean true or false false
l2_cache-size Set L2 cache size in bytes integer 512KB, 1MB,
2MB, 4MB
0x400000
l2_cache-state_modelled
Set whether L2 cache has stateful
implementation
boolean true or false false
PERIPHBASE Base address of peripheral memory space. integer - 0x13080000 b
a. Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation
is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device
accuracy is required.
b. If you are using the ARMCortexA15xnCT component on an VE model platform, this parameter is set automatically to
0x1F000000 and is not visible in the parameter list.
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