Fast Models Reference Manual - ARM Information Center

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Emulation Baseboard Model: Platform and Components Table 7-7 EBVisualisation configuration parameters (continued) Parameter name Description Type Allowed value Default value cpu_name CPU name displayed in window title string Real-Time System Model CLCD %cpu% daughter_led_count daughter_user_switch_ count Set to non-zero to display up to 32 LEDs. See daughter_leds in Table 7-6 on page 7-10. Set this parameter to display up to 32 switches. See daughter_user_switches in Table 7-6 on page 7-10. integer 0-32 0 integer 0-32 0 a. See the header file, %PVLIB_HOME%\components\KeyCode.h, for a list of ATKeyCode values. On Linux, use $PVLIB_HOME/components/KeyCode.h. b. This is equivalent to the left Alt key, so pressing Left Alt and Left Ctrl simultaneously toggles the mouse display. Note Setting the rate_limit-enable parameter to true (the default) prevents the simulation from running too fast on fast workstations and enables timing loops and mouse actions to work correctly. The overall simulation speed, however, is reduced. If your priority is high simulation speed, set rate_limit-enable to false. 7.4.4 Registers The EBVisualisation component has no registers. 7.4.5 Debug Features The EBVisualisation component has no debug features. 7.4.6 Verification and testing The EBVisualisation component has been tested by use as an I/O device for booting Linux and other operating systems. 7.4.7 Performance Use of elements in the status bar are not expected to significantly affect the performance of a PV system. However, applications that make heavy use of re-drawing the contents of the frame buffer incur overhead through GUI interactions on the host OS. 7.4.8 Library dependencies The MPSVisualisation component relies on the Simple DirectMedia Layer (SDL) libraries, specifically libSDL-1.2.so.0.11.2. This library is bundled with the Model Library and is also available as a rpm for Red Hat Enterprise Linux. See http://www.libsdl.org/ for more information on SDL. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-12 ID051811 Non-Confidential
Emulation Baseboard Model: Platform and Components 7.5 EB_SysRegs component The EB system registers component is a programmer’s view model of the EB baseboard status and system control registers. For a detailed description of the behavior of the component, refer to the hardware documentation. See the RealView Emulation Baseboard User Guide (Lead Free). Figure 7-4 shows a view of the component in System Canvas. This component is written in LISA+. Figure 7-4 EB_SysRegs in System Canvas 7.5.1 Ports Table 7-8 provides a brief description of the EB_SysRegs component ports. Refer to the hardware documentation for more details. Name Port Protocol Type Description Table 7-8 EB_SysRegs ports pvbus PVBus slave slave port for connection to PV bus master/decoder clk_in_24mhz ClockSignal slave reference clock for internal counter register clk_in_100hz ClockSignal slave reference clock for internal counter register osc0 ICS307Configuration master settings for the ICS307 OSC0 osc1 ICS307Configuration master settings for the ICS307 OSC1 osc2 ICS307Configuration master settings for the ICS307 OSC2 osc3 ICS307Configuration master settings for the ICS307 OSC4 osc4 ICS307Configuration master settings for the ICS307 OSC5 boot_control ValueState master passes the value of the boot switch to the EBRemapper component a ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-13 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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