Fast Models Reference Manual - ARM Information Center

Processor Components
Table 4-7 ARMCortexA9UPCT ports (continued)
Name Port protocol Type Description
standbywfi[0] Signal master Indicates if a processor is in WFI state.
teinit[0] Signal slave Initialize to take exceptions in Thumb state after a reset.
ticks[0] InstructionCount master Processor instruction count for visualization.
vinithi[0] Signal slave Initialize with high vectors enabled after a reset.
4.4.2 Additional protocols
The ARMCortexA9UPCT component has no additional protocols.
4.4.3 Parameters
Table 4-8 lists the parameters set at the processor level for the ARMCortexA9UPCT
component.
Table 4-8 ARMCortexA9UPCT parameters a
Parameter Description Type
Allowed
value
Default
value
CLUSTER_ID CPU cluster ID value. integer 0-15 0
device-accurate-tlb
dcache-state_modelled
icache-state_modelled
Specify whether all TLBs
are modeled.
Set whether D-cache has
stateful implementation.
Set whether I-cache has
stateful implementation.
boolean true/false false b
boolean true/false false
boolean true/false false
a. For the ARMCortexA9UP processor, the instance name for the processor consists of the normal instance
name (in the provided examples, cortile.core) with a suffix of cpu0. In the example Cortex-A9 platform the
instance name is cortile.core.cpu0
b. Specifying false models enables modeling a different number of TLBs if this improves simulation
performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is
almost always sufficient. Specify true if device accuracy is required.
Table 4-9 provides a description of the CPU configuration parameters for the
ARMCortexA9UPCT component.
Table 4-9 ARMCortexA9UPCT individual processor parameters
Parameter Description Type
Allowed
value
Default
value
CFGEND Initialize to BE8 endianness. boolean true/false false
CFGNMFI
CP15SDISABLE
Enable non-maskable fast interrupts
on startup.
Initialize to disable access to some
CP15 registers.
boolean true/false false
boolean true/false false
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