Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components saveFlashFile(FlashLoader*) : uint32 Save the flash contents to a file. Parameters Table 5-108 provides a description of the configuration parameters for the FlashLoader component. Table 5-108 FlashLoader configuration parameters Parameter name Description Type Allowed value Default value fname fnameWrite Path to host file used to initialize flash contents. The file can be gzip compressed. Path to the flash contents file which is written when model exits String - [empty string] String - [empty string] Registers The FlashLoader component has no registers. Debug features The FlashLoader component has no debug features. Verification and testing The FlashLoader component has been tested as part of the VE example system using VE test suites and by booting operating systems. Performance The FlashLoader component is not expected to significantly affect the performance of a PV system. Library dependencies The FlashLoader component has no dependencies on external libraries. 5.4.39 IntelStrataFlashJ3 component The IntelStrataFlashJ3 component provides an efficient implementation of a NOR Flash memory type device. In normal usage, the device acts as Read Only Memory (ROM) whose contents can be determined either by programming using the flashloader port or by using standard flash programming software run on the model, such as the ARM Firmware Suite. The size of the flash is determined by a startup parameter, size. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-133 ID051811 Non-Confidential
Peripheral and Interface Components The IntelStrataFlashJ3 component implementation is approximately that of the Intel part used in the VE development board. The component is effectively organized as a bank of two 16bit Intel Flash components forming a 32bit component that may be read or programmed in parallel. The component supports all hardware behavior except for the following: • protection register • enhanced configuration register • unique device identifier • one time programmable cells • block locking, which is silently ignored • suspend/resume, which is silently ignored • status interrupt line. All block operations are atomic. This means that the status register state machine status bit always reads 1, ready. For further information on the behavior of the hardware, refer to the Intel datasheet for the Intel StrataFlash Memory (J3). See , http://downloadcenter.intel.com/ Figure 5-59 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-59 IntelStrataFlashJ3 in System Canvas Ports The table below provides a brief description of the IntelStrataFlashJ3 component ports. Name Port protocol Type Description Table 5-109 IntelStrataFlashJ3 ports flashloader FlashLoaderPort Slave Allows a FlashLoader component to initialize the flash contents from a binary file pvbus PVBus Slave Slave port for connection to PV bus master/decoder mbs_control PVBusSlaveControl Master Internal control mem_port PVDevice Slave Additional protocols The IntelStrataFlashJ3 component has one additional protocol, FlashLoaderPort. See FlashLoaderPort on page 5-132. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-134 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Peripheral and Interface Components
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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Glossary DSR DTR EB GIC GPIO I/O KM
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Fast Models Reference Manual - ARM Information Center

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