Fast Models Reference Manual - ARM Information Center

Processor Components
4.7.2 Additional protocols
The ARMCortexA5CT component has no additional protocols.
4.7.3 Parameters
Table 4-16 lists the parameters set at the processor level for the ARMCortexA5CT component.
Table 4-16 ARMCortexA5CT parameters
Parameter Description Type
Allowed
value
Default
value
CLUSTER_ID CPU cluster ID value. integer 0-15 0
device-accurate-tlb
dcache-state_modelled
icache-state_modelled
Specify whether all TLBs
are modeled.
Set whether D-cache has
stateful implementation.
Set whether I-cache has
stateful implementation.
boolean true/false false a
boolean true/false false
boolean true/false false
a. Specifying false models enables modeling a different number of TLBs if this improves simulation
performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is
almost always sufficient. Specify true if device accuracy is required.
Table 4-17 provides a description of the CPU configuration parameters for the
ARMCortexA5CT component.
Table 4-17 ARMCortexA5CT individual processor parameters
Parameter Description Type
Allowed
value
Default
value
CFGEND Initialize to BE8 endianness. boolean true/false false
CFGNMFI
CP15SDISABLE
TEINIT
Enable non-maskable fast interrupts
on startup.
Initialize to disable access to some
CP15 registers.
Thumb exception enable. The default
has exceptions including reset
handled in ARM state.
boolean true/false false
boolean true/false false
boolean true/false false
VINITHI Initialize with high vectors enabled. boolean true/false false
POWERCTLI Default power control state for CPU. integer 0-3 0
ase-present a
Set whether model has NEON
support.
boolean true/false true
semihosting-cmd_line
Command line available to
semihosting SVC calls.
string
no limit
except
memory
[empty
string]
semihosting-debug b
Enable debug output of semihosting
SVC calls.
boolean true/false false
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