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Fast Models Reference Manual - ARM Information Center

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Processor Components<br />

Table 4-13 <strong>ARM</strong>CortexA5MPxnCT parameters (continued)<br />

Parameter Description Type<br />

Allowed<br />

value<br />

Default<br />

value<br />

dcache-state_modelled<br />

Set whether D-cache has stateful<br />

implementation.<br />

boolean true/false false<br />

device-accurate-tlb Specify whether all TLBs are modeled. boolean true/false false b<br />

dic-spi_count<br />

Number of shared peripheral interrupts<br />

implemented.<br />

integer<br />

0-223, in<br />

increments of<br />

32<br />

64<br />

icache-state_modelled<br />

Set whether I-cache has stateful<br />

implementation.<br />

boolean true/false false<br />

a. If you are using the <strong>ARM</strong>CortexA5MPxnCT component on an VE model platform, this parameter is set automatically to<br />

0x1F000000 and is not visible in the parameter list.<br />

b. Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The<br />

simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true<br />

if device accuracy is required.<br />

Table 4-14 provides a description of the configuration parameters for each<br />

<strong>ARM</strong>CortexA5MPxnCT component processor. These parameters are set individually for each<br />

processor you have in your system.<br />

Table 4-14 <strong>ARM</strong>CortexA5MPxnCT individual processor parameters<br />

Parameter Description Type<br />

Allowed<br />

value<br />

Default<br />

value<br />

CFGEND Initialize to BE8 endianness. boolean true/false false<br />

CFGNMFI<br />

CP15SDISABLE<br />

SMPnAMP<br />

TEINIT<br />

Enable non-maskable fast interrupts on<br />

startup.<br />

Initialize to disable access to some CP15<br />

registers.<br />

Set whether the processor is part of a<br />

coherent domain.<br />

Thumb exception enable. The default<br />

has exceptions including reset handled<br />

in <strong>ARM</strong> state.<br />

boolean true/false false<br />

boolean true/false false<br />

boolean true/false false<br />

boolean true/false false<br />

VINITHI Initialize with high vectors enabled. boolean true/false false<br />

POWERCTLI Default power control state for CPU. integer 0-3 0<br />

ase-present a<br />

Set whether the model has NEON<br />

support.<br />

boolean true/false true<br />

dcache-size Set D-cache size in bytes. integer 4KB, 8KB,<br />

16KB, 32KB,<br />

or 64KB<br />

icache-size Set I-cache size in bytes. integer 4KB, 8KB,<br />

16KB, 32KB,<br />

or 64KB<br />

0x8000<br />

0x8000<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 4-29<br />

ID051811<br />

Non-Confidential

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