Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Registers Table 5-101 provides a description of the configuration registers for the BP147_TZPC component. Table 5-101 BP147_TZPC registers Register name Offset Access Description R0SIZE 0x000 read/write Secure RAM region size register DECPROT0Stat 0x800 read only Decode protection 0 status register DECPROT0Set 0x804 write only Decode protection 0 set register DECPROT0Clr 0x808 write only Decode protection 0 clear register DECPROT1Stat 0x80C read only Decode protection 1 status register DECPROT1Set 0x810 write only Decode protection 1 set register DECPROT1Clr 0x814 write only Decode protection 1 clear register DECPROT2Stat 0x818 read only Decode protection 2status register DECPROT2Set 0x81C write only Decode protection 2 set register DECPROT2Clr 0x820 write only Decode protection 2 clear register Debug features The BP147_TZPC component has no debug features. Verification and testing The BP147_TZPC has been tested using a unit test suite. Performance The BP147_TZPC component is not expected to significantly affect the performance of a PV system. Library dependencies The BP147_TZPC component has no dependencies on external libraries. 5.4.35 AndGate component The AndGate component implements a logical AND of two Signal input ports to generate a single output Signal. You can use this, for example, to combine two interrupt signals. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-127 ID051811 Non-Confidential
Peripheral and Interface Components Figure 5-55 shows a view of the component in System Canvas. This component is written in LISA. Figure 5-55 AndGate in System Canvas Ports Table 5-102 provides a brief description of the AndGate component ports. Table 5-102 AndGate ports Name Port protocol Type Description input[0] Signal Slave First input signal input[1] Signal Slave Second input signal output Signal Master Combined output signal Additional protocols The AndGate component has no additional protocols. Parameters The AndGate component has no parameters. Registers The AndGate component has no registers. Debug features The AndGate component has no debug features. Verification and testing The AndGate component has been tested as part of the VE example system using VE test suites and by booting operating systems. Performance The AndGate component is not expected to significantly affect the performance of a PV system. Library dependencies The AndGate component has no dependencies on external libraries. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-128 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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