Fast Models Reference Manual - ARM Information Center

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Versatile Express Model: Platform and Components 6.7.6 Timing considerations The Real-Time System Models provide an environment that enables running software applications in a functionally-accurate simulation. However, because of the relative balance of fast simulation speed over timing accuracy, there are situations where the models might behave unexpectedly. When code interacts with real world devices like timers and keyboards, data arrives in the modeled device in real-world (or wall-clock) time, but simulation time can be running much faster than the wall clock. This means that a single keypress might be interpreted as several repeated key presses, or a single mouse click incorrectly becomes a double click. The VE RTSMs provide the Rate Limit feature to match simulation time to match wall-clock time. Enabling Rate Limit, either by using the Rate Limit button in the CLCD display, or the rate_limit-enable model instantiation parameter, forces the model to run at wall-clock time. This avoids issues with two clocks running at significantly different rates. For interactive applications, ARM recommends enabling Rate Limit. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 6-21 ID051811 Non-Confidential
Chapter 7 Emulation Baseboard Model: Platform and Components This chapter describes components of Fast Models that are specific to the EB system model of the hardware platform. It contains the following sections: • About the Emulation Baseboard components on page 7-2 • Emulation Baseboard memory map on page 7-3 • Emulation Baseboard parameters on page 7-6 • EBVisualisation component on page 7-9 • EB_SysRegs component on page 7-13 • EBCortexA9_SysRegs component on page 7-18 • TSC2200 component on page 7-20 • Other Emulation Baseboard components on page 7-22 • Differences between the EB hardware and the system model on page 7-23. Note Using the visualization component can reduce simulation performance on some workstations. The simulation speed is affected by the setting of the rate_limit-enable parameter as described in Parameters on page 7-11. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 7-1 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Glossary DSR DTR EB GIC GPIO I/O KM
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