Fast Models Reference Manual - ARM Information Center

Processor Components
Name Port protocol Type Description
pv_ppbus_m PVBus master master port for memory accesses on the
External Private Peripheral Bus
sleepdeep Signal master indicates that the processor is in deep sleep
sleeping Signal master indicates that the processor is in sleep
stcalib Value slave SysTick calibration value
stclk ClockSignal slave reference clock input for SysTick
sysreset Signal slave asynchronous reset signal input
sysresetreq Signal master system reset request
Table 4-25 ARMCortexM3CT ports (continued)
ticks InstructionCount master output that can be connected to a visualization
component
4.11.2 Additional protocols
The ARMCortexM3CT component has no additional protocols.
4.11.3 Parameters
Table 4-26 provides a description of the configuration parameters for the ARMCortexM3CT
component.
Table 4-26 ARMCortexM3CT parameters
Parameter Description Type
Allowed
value
Default
value
LVL_WIDTH
Number of bits of interrupt
priority.
integer 3-8 3
NUM_IRQ Number of user interrupts. integer 1-240 16
NUM_MPU_REGION Number of MPU regions. integer 0,8 8
BIGENDINIT
Initialize processor to big endian
mode
boolean true/false false
semihosting-cmd_line a
Command line available to
semihosting SVC calls.
string
no limit except
memory
[empty
string]
semihosting-debug
semihosting-enable
Enable debug output of
semihosting SVC calls.
Enable semihosting SVC traps.
Caution
Applications that do not use
semihosting must set this
parameter to false.
boolean true/false false
boolean true/false true
semihosting-Thumb_SVC
Thumb SVC number for
semihosting.
integer 8 bit integer 0xAB
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