Fast Models Reference Manual - ARM Information Center

Processor Components
4.6.1 Ports
Table 4-12 provides a brief description of the ports in the ARMCortexA5MPxnCT component.
Refer to the processor technical reference manual for more details.
Name Port protocol Type Description
acp_s PVBus slave Slave channel
Table 4-12 ARMCortexA5MPxnCT ports
cfgend[0-3] Signal slave Initialize to BE8 endianness after a
reset.
cfgnmfi[0-3] Signal slave Enable non-maskable fast interrupts
after a reset.
cfgsdisable Signal slave Disable write access to some GIC
registers.
clk_in ClockSignal slave Main CPU clock input.
clusterid Value slave Value read in MPIDR register.
cp15sdisable[0-3] Signal slave Disable write access to some cp15
registers.
event Signal peer Event input and output for wakeup from
WFE. This port amalgamates the
EVENTI and EVENT0 signals that are
present on hardware.
filteren Signal slave Enable filtering of address ranges
between master bus ports.
filterend Value slave End of region mapped to pvbus_m1.
filterstart Value slave Start of region mapped to pvbus_m1.
fiq[0-3] Signal slave Processor FIQ signal input.
irq[0-3] Signal slave Processor IRQ signal input.
ints[0-223] Signal slave Shared peripheral interrupts.
periphbase Value slave Base of private peripheral region.
periphclk_in ClockSignal slave Timer/watchdog clock rate.
periphreset Signal slave Timer and GIC reset signal.
pmuirq[0-3] Signal master Performance Monitoring Unit (PMU)
interrupt signal.
pvbus_m0 PVBus master AXI master 0 bus master channel.
pvbus_m1 PVBus master AXI master 1 bus master channel.
pwrctli[0-3] Value slave Reset value for SCU CPU status
register.
pwrctlo[0-3] Value master SCU CPU status register bits.
reset[0-3] Signal slave Individual processor reset signal.
scureset Signal slave SCU reset signal.
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