Fast Models Reference Manual - ARM Information Center

More documents

Recommendations

Info

Peripheral and Interface Components Parameters Table 5-93 provides a description of the configuration parameters for the TZMPU component. Table 5-93 TZMPU configuration parameters Parameter name Description Type Allowed value Default value numRegions Number of memory regions Integer 2 to 16, in increments of 1 16 axiAddrWidth AXI address width, in bits Integer 32 to 64, in increments of 1 bit 32 Registers Table 5-94 provides a description of the configuration registers for the TZMPU component. Table 5-94 TZMPU registers Register name Offset Access Description configuration 0x000 read only Defines AXI address width and number of regions. action 0x004 read/write Action for access permission failures. lockdown_range 0x008 read/write Region lockdown range. lockdown_enable 0x00C read/write Region lockdown select. int_status 0x010 read only Indicates status of permission failures. int_clear 0x014 write only Clear unserviced interrupts. fail_address_low 0x020 read only Low order 32 bits of address failed. fail_address_high 0x024 read only High order 32 bits of address failed. fail_control 0x028 read only Access type of failed accesses. fail_id 0x02C read only Master AXI ID of failed access. region_base_lo_0 0x100 read only, or read/write a region_base_hi_0 0x104 read only, or read/write a region_attr_sz_0 0x108 read only, or read/write a region_base_lo_1 0x110 read only, or read/write a Protection region 0 base low address. Protection region 0 base high address. Protection region 0 size. Protection region 1 base low address. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-119 ID051811 Non-Confidential
Peripheral and Interface Components Table 5-94 TZMPU registers (continued) Register name Offset Access Description region_base_hi_1 0x114 read only, or read/write a region_attr_sz_1 0x118 read only, or read/write a Protection region 1 base high address. Protection region 1 size. … … … … region_base_lo_15 0x1F0 read only, or read/write a region_base_hi_15 0x1F4 read only, or read/write a region_attr_sz_15 0x1F8 read only, or read/write a Protection region 15 base low address. Protection region 15 base high address. Protection region 15 size. itcr 0xE00 read/write Integration test control register. itip 0xE04 read only Integration test input register. itop 0xE08 read/write Integration test output register. periph_id_0 0xFE0 read only Peripheral identification register. periph_id_1 0xFE4 read only Peripheral identification register. periph_id_2 0xFE8 read only Peripheral identification register. periph_id_3 0xFEC read only Peripheral identification register. pcell_id_0 0xFF0 read only PrimeCell identification register 0. pcell_id_1 0xFF4 read only PrimeCell identification register 1. pcell_id_2 0xFF8 read only PrimeCell identification register 2. pcell_id_3 0xFFC read only PrimeCell identification register 3. a. Regions specified in the lockdown_range register are locked down and are read only, otherwise they are read/write. Debug features The TZMPU component has no debug features. Verification and testing The TZMPU component has been tested separately using its own test suite. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-120 ID051811 Non-Confidential
Page 1 and 2:
Fast Models Version 6.1 Reference M
Page 3 and 4:
Contents Fast Models Reference Manu
Page 5 and 6:
Preface This preface introduces the
Page 7 and 8:
Preface Typographical conventions T
Page 9 and 10:
Preface Feedback ARM welcomes feedb
Page 11 and 12:
Introduction 1.1 About the componen
Page 13 and 14:
Accuracy and Functionality 2.1 Mode
Page 15 and 16:
Accuracy and Functionality 2.2.2 Pe
Page 17 and 18:
Accuracy and Functionality 2. For a
Page 19 and 20:
Accuracy and Functionality Fast Mod
Page 21 and 22:
Signaling and Clocking Protocols 3.
Page 23 and 24:
Signaling and Clocking Protocols 3.
Page 25 and 26:
Signaling and Clocking Protocols Pa
Page 27 and 28:
Signaling and Clocking Protocols Ve
Page 29 and 30:
Chapter 4 Processor Components This
Page 31 and 32:
Processor Components 4.2 ARMCortexA
Page 33 and 34:
Processor Components InstructionCou
Page 35 and 36:
Processor Components c. This is a m
Page 37 and 38:
Page 39 and 40:
Processor Components Table 4-4 ARMC
Page 41 and 42:
Page 43 and 44:
Processor Components 4.3.9 Library
Page 45 and 46:
Page 47 and 48:
Processor Components a. The ase-pre
Page 49 and 50:
Processor Components 4.4.8 Performa
Page 51 and 52:
Processor Components 4.5.3 Paramete
Page 53 and 54:
Processor Components The debugger m
Page 55 and 56:
Processor Components 4.6.1 Ports Ta
Page 57 and 58:
Processor Components Table 4-13 ARM
Page 59 and 60:
Processor Components 4.6.5 Caches T
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
Processor Components 4.7.8 Performa
Page 67 and 68:
Processor Components Name Port Prot
Page 69 and 70:
Page 71 and 72:
Processor Components b. Currently i
Page 73 and 74:
Processor Components 4.9 ARMCortexR
Page 75 and 76:
Page 77 and 78:
Processor Components 4.9.9 Library
Page 79 and 80:
Processor Components Name Port prot
Page 81 and 82:
Processor Components The debugger m
Page 83 and 84:
Processor Components 4.11 ARMCortex
Page 85 and 86:
Page 87 and 88:
Processor Components 4.12 ARMv7A -
Page 89 and 90:
Processor Components pwrctli[0-3] V
Page 91 and 92:
Processor Components Table 4-29 Pro
Page 93 and 94:
Processor Components Cache geometry
Page 95 and 96:
Processor Components Note In the vi
Page 97 and 98:
Processor Components Message config
Page 99 and 100:
Processor Components All entries in
Page 101 and 102:
Processor Components 4.13.3 Paramet
Page 103 and 104:
Processor Components Memory The ARM
Page 105 and 106:
Page 107 and 108:
Processor Components Memory The ARM
Page 109 and 110:
Page 111 and 112:
Processor Components 4.15.5 Debug f
Page 113 and 114:
Processor Components 4.16 ARM926CT
Page 115 and 116:
Processor Components Registers All
Page 117 and 118:
Processor Components • Data/Instr
Page 119 and 120:
Processor Components DMA DMA is cur
Page 121 and 122:
Processor Components Table 4-47 Cor
Page 123 and 124:
Peripheral and Interface Components
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Page 189 and 190: Peripheral and Interface Components
Page 239: Peripheral and Interface Components
Page 291 and 292:
Page 293 and 294:
Versatile Express Model: Platform a
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
Chapter 7 Emulation Baseboard Model
Page 315 and 316:
Emulation Baseboard Model: Platform
Page 317 and 318:
Page 319 and 320:
Page 321 and 322:
Page 323 and 324:
Page 325 and 326:
Page 327 and 328:
Page 329 and 330:
Page 331 and 332:
Page 333 and 334:
Page 335 and 336:
Page 337 and 338:
Page 339 and 340:
Microcontroller Prototyping System:
Page 341 and 342:
Page 343 and 344:
Page 345 and 346:
Page 347 and 348:
Page 349 and 350:
Page 351 and 352:
Page 353 and 354:
Page 355 and 356:
AEM ARMv7-A specifics A.1 Boundary
Page 357 and 358:
AEM ARMv7-A specifics When paramete
Page 359 and 360:
AEM ARMv7-A specifics When stepping
Page 361 and 362:
AEM ARMv7-A specifics A.2 Debug arc
Page 363 and 364:
AEM ARMv7-A specifics A.3 IMPLEMENT
Page 365 and 366:
AEM ARMv7-A specifics A.4 Trace The
Page 367 and 368:
Glossary DSR DTR EB GIC GPIO I/O KM
show all

Fast Models Reference Manual - ARM Information Center

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?