Fast Models Reference Manual - ARM Information Center

Microcontroller Prototyping System: Platform and Components
Table 8-1 Overview of MPS memory map (continued)
Description Modeled Address range
LIN Partial a 0x4FFD0000–0x4FFDFFFF
Ethernet Partial a 0x4FFE0000–0x4FFEFFFF
Video Yes 0x4FFF0000–0x4FFFFFFF
External AHB interface to DUT FPGA Yes 0x50000000–0x5FFFFFFF
DMC Yes 0x60000000–0x9FFFFFFF
SMC Yes 0xA0000000–0xAFFFFFFF
Private Peripheral Bus Yes 0xE0000000–0xE00FFFFF
System bus interface to DUT FPGA Yes 0xE0100000–0xFFFFFFFF
a. This model is represented by a register bank and has no functionality beyond this.
Note
A Bus Error is generated for accesses to memory areas not shown above.
Any memory device that does not occupy the total region is aliased within that region.
8.2.1 MPS registers
This section describes the MPS memory-mapped registers.
CPU system registers
Table 8-2 provides a description of the CPU system registers.
Table 8-2 MPS CPU system registers
Register name Address Access Description
SYS_ID 0x1F000000 read/write Board and FPGA identifier
SYS_MEMCFG 0x1F000004 read/write Memory remap and alias
SYS_SW 0x1F000008 read/write Indicates user switch settings
SYS_LED 0x1F00000C read/write Sets LED outputs
SYS_TS 0x1F000010 read/write TouchScreen register
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