Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Figure 5-55 shows a view of the component in System Canvas.
This component is written in LISA.
Figure 5-55 AndGate in System Canvas
Ports
Table 5-102 provides a brief description of the AndGate component ports.
Table 5-102 AndGate ports
Name Port protocol Type Description
input[0] Signal Slave First input signal
input[1] Signal Slave Second input signal
output Signal Master Combined output signal
Additional protocols
The AndGate component has no additional protocols.
Parameters
The AndGate component has no parameters.
Registers
The AndGate component has no registers.
Debug features
The AndGate component has no debug features.
Verification and testing
The AndGate component has been tested as part of the VE example system using VE test suites
and by booting operating systems.
Performance
The AndGate component is not expected to significantly affect the performance of a PV system.
Library dependencies
The AndGate component has no dependencies on external libraries.
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