Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Performance The TZMPU component is not expected to significantly affect the performance of a PV system. Library dependencies The TZMPU component has no dependencies on external libraries. 5.4.31 RemapDecoder The RemapDecoder component provides the low memory flash/RAM remap behavior of the example systems. Figure 5-51 shows a view of the component in System Canvas. This model is written in LISA+. Figure 5-51 RemapDecoder in System Canvas Ports The table below provides a brief description of the ports of the RemapDecoder component. Refer to the VE hardware documentation for more details. Name Port protocol Type Description Table 5-95 RemapDecoder ports input PVBus Slave For connection to PV bus master/decoder output_remap_set PVBus Master For connection to a component addressable with remap set output_remap_clear PVBus Master For connection to a component addressable with remap clear remap StateSignal Slave Input allowing control of remap state control TZSwitchControl Internal port. Not for use. Additional protocols The RemapDecoder component has no additional protocols. Parameters The RemapDecoder component has no parameters. Registers The RemapDecoder component has no registers ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-121 ID051811 Non-Confidential
Peripheral and Interface Components Debug features The RemapDecoder component has no debug features. Verification and testing The RemapDecoder component has been tested as part of the VE example system using VE test suites and by booting operating systems. Performance The RemapDecoder component is not expected to significantly affect the performance of a PV system. Library dependencies The RemapDecoder component has no dependencies on external libraries. 5.4.32 BP135_AXI2APB component The BP135_AXI2APB component is a programmer’s view model of the ARM AXI2APB Bridge peripheral. The component, when configured by another component such as the BP141_TZPC, allows control of secure access to up to 16 PrimeCell peripherals. For further information, refer to the component documentation. See PrimeCell Infrastructure AMBA ® 3 AXI to AMBA 3 APB Bridge (BP135) Revision: r0p0 Technical Overview. The PVBus makes no distinction between AXI and APB bus protocols. For simple models, you do not need to use a bridge peripheral when connecting devices to a CPU. Figure 5-52 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-52 BP135_AXI2APB in System Canvas ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-122 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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Fast Models Reference Manual - ARM Information Center

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