Fast Models Reference Manual - ARM Information Center

Processor Components
Table 4-24 ARMCortexM4CT parameters (continued)
Parameter Description Type
Allowed
value
Default
value
semihosting-debug
semihosting-enable
Enable debug output of
semihosting SVC calls.
Enable semihosting SVC traps.
Caution
Applications that do not use
semihosting must set this
parameter to false.
boolean true/false false
boolean true/false true
semihosting-Thumb_SVC
Thumb SVC number for
semihosting.
integer 8 bit integer 0xAB
semihosting-heap_base Virtual address of heap base. integer 0x00000000 -
0xFFFFFFFF
semihosting-heap_limit Virtual address of top of heap. integer 0x00000000 -
0xFFFFFFFF
0x0
0x10700000
semihosting-stack_base
Virtual address of base of
descending stack.
integer 0x00000000 -
0xFFFFFFFF
0x10700000
semihosting-stack_limit Virtual address of stack limit. integer 0x00000000 -
0xFFFFFFFF
0x10800000
vfp-present
Set whether the model has VFP
support
boolean true/false true
4.10.4 Registers
The ARMCortexM4CT component provides the registers specified by the technical reference
manual for the Cortex-M4. Exceptions are listed in the section Differences between the CT
model and RTL implementations on page 4-53.
4.10.5 Caches
The ARMCortexM4CT component does not implement any caches.
4.10.6 Debug features
The ARMCortexM4CT component exports a CADI debug interface.
Registers
All processor and implemented registers are visible in the debugger. See the processor technical
reference manual for a detailed description of available registers.
Breakpoints
There is direct support for:
• single address unconditional instruction breakpoints
• unconditional instruction address range breakpoints
• single address unconditional data breakpoints.
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