Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components b. See PL080_DMAC_DmaPortProtocol on page 5-67. Additional protocols The PL022_SSP component has no additional protocols. Parameters The PL022_SSP component has no parameters. Registers Table 5-36 provides a description of the configuration registers for the PL022_SSP component. Table 5-36 PL022_SSP registers Register name Offset Access Description SSPCR0 0x000 read/write Control register 0. SSPCR1 0x004 read/write Control register 1. SSPDR 0x008 read/write FIFO data. SSPSR 0x00C read only Status. SSPCPSR 0x010 read/write Clock prescale. SSPIMSC 0x014 read/write Interrupt mask set/clear. SSPRIS 0x018 read only Raw interrupt status. SSPMIS 0x01C read only Masked interrupt status. SSPICR 0x020 write only Interrupt clear. SSPDMACR 0x024 read/write DMA control. SSPeriphID0 0xFE0 read only Peripheral ID bits 7:0. SSPeriphID1 0xFE4 read only Peripheral ID bits 15:8. SSPeriphID2 0xFE8 read only Peripheral ID bits 23:16. SSPeriphID3 0xFEC read only Peripheral ID bits 31:24. SSPPCellID0 0xFF0 read only PrimeCell ID bits 7:0. SSPPCellID01 0xFF4 read only PrimeCell ID bits 15:8. SSPPCellID 0xFF8 read only PrimeCell ID bits 23:16. SSPPCellID3 0xFFC read only PrimeCell ID bits 31:24. Debug features The PL022_SSP component has no debug features. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-49 ID051811 Non-Confidential
Peripheral and Interface Components Verification and testing The functions of the PL022_SSP component have been tested individually using a tailored test suite. The component has not been validated against a target operating system, but improved support is expected in the next release. Performance The PL022_SSP component is not expected to significantly affect the performance of a PV system. Library dependencies The PL022_SSP component has no dependencies on external libraries. 5.4.6 PL030_RTC component The PL030_RTC component is a programmer's view model of the PL030_RTC PrimeCell. For a detailed description of the behavior of the PrimeCell, read the technical reference manual. See the ARM PrimeCell Real Time Clock (PL030) Technical Reference Manual. Figure 5-25 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-25 PL030_RTC in System Canvas Ports Table 5-37 provides a brief description of the ports. See the PL030 documentation for more details. Name Port protocol Type Description Table 5-37 PL030_RTC ports pvbus PVBus Slave Slave port for connection to PV bus master/decoder. intr Signal Master Interrupt signaling. clock ClockSignal Slave Clock input, typically 1MHz, driving master count rate. Additional protocols The PL030_RTC component has no additional protocols. Parameters The PL030_RTC component has no parameters. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-50 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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