Fast Models Reference Manual - ARM Information Center

Processor Components
Name Port protocol Type Description
reset Signal slave asynchronous reset signal input (not debug
components)
sleepdeep Signal master indicates that the processor is in deep sleep
sleeping Signal master indicates that the processor is in sleep
stcalib Value slave SysTick calibration value
stclk ClockSignal slave reference clock input for SysTick
sysreset Signal slave asynchronous reset signal input
sysresetreq Signal master system reset request
Table 4-23 ARMCortexM4CT ports (continued)
ticks InstructionCount master output that can be connected to a visualization
component
dbgen a Signal slave enable hardware debugger access
fpudisable Signal slave disable FPU on next reset
mpudisable Signal slave disable MPU on next reset
fpxxc Value master cumulative exception flags from the Floating
Point Status and Control Register (FPSCR).
This value port combines the five RTL signals
FPIXC, FPIDC, FPOFC, FPUFC, FPDZC and
FPIOC.
a. Since the CT model does not provide a DAP port or halting debug capability, this signal is ignored.
4.10.2 Additional protocols
The ARMCortexM4CT component has no additional protocols.
4.10.3 Parameters
Table 4-24 provides a description of the configuration parameters for the ARMCortexM4CT
component.
Table 4-24 ARMCortexM4CT parameters
Parameter Description Type
Allowed
value
Default
value
BIGENDINIT
Initialize processor to big endian
mode
boolean true/false false
BB_PRESENT Enable bitbanding boolean true/false true
LVL_WIDTH
Number of bits of interrupt
priority.
integer 3-8 3
NUM_IRQ Number of user interrupts. integer 1-240 16
NUM_MPU_REGION Number of MPU regions. integer 0,8 8
semihosting-cmd_line
Command line available to
semihosting SVC calls.
string
no limit except
memory
[empty
string]
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