Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Ports
Table 5-58 provides a brief description of the ports. See also the ARM PrimeCell Color LCD
Controller (PL111) Technical Reference Manual.
Name Port protocol Type Description
Table 5-58 PL111_CLCD ports
pvbus PVBus Slave Slave port for connection to PV bus
master/decoder.
intr Signal Master Interrupt signaling for flyback events.
clk_in ClockSignal Slave Master clock input, typically 24MHz, to
drive pixel clock timing.
display LCD Master Connection to visualization component.
See Visualization Library on
page 5-149.
control Value Slave Auxiliary control register 1.
pvbus_m PVBus Master DMA port for video data.
Additional protocols
The PL111_CLCD component has no additional protocols.
Parameters
Table 5-59 provides a description of the configuration parameters for the PL111_CLCD
component.
Table 5-59 PL111_CLCD configuration parameters
Parameter name Description Type
Allowed
value
Default
value
pixel_double_limit
Sets a threshold in
horizontal pixels,
below which pixels
sent to the
framebuffer are
doubled in size
horizontally and
vertically.
Integer - 300
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