Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Ports
Table 5-39 provides a brief description of the ports. See the PL031 RTC documentation for
further details.
Name Port protocol Type Description
Table 5-39 PL031_RTC ports
pvbus PVBus Slave Slave port for connection to PV bus
master/decoder.
intr Signal Master Interrupt signaling.
clock ClockSignal Slave Clock input, typically 1MHz, driving
master count rate.
Additional protocols
The PL031_RTC component has no additional protocols.
Parameters
The PL031_RTC component has no parameters.
Registers
Table 5-40 provides a description of the configuration registers for the PL031_RTC component.
Table 5-40 PL031_RTC registers
Register
name
Offset Access Description
RTCDR 0x000 read only Data register.
RTCMR 0x004 read/write Match register.
RTCLR 0x008 read/write Load register.
RTCCR 0x00C read/write Control register.
RTCIMSC 0x010 read/write Interrupt mask set and clear
register.
RTCRIS 0x014 read only Raw interrupt status
register.
RTCMIS 0x018 read only Masked interrupt status
register.
RTCIRC 0x01C write only Interrupt clear register a .
RTCPeriphID0 0xFE0 read only Peripheral ID register a .
RTCPeriphID1 0xFE4 read only Peripheral ID register a .
RTCPeriphID2 0xFE8 read only Peripheral ID register a .
RTCPeriphID3 0xFEC read only Peripheral ID register a .
RTCPCellID0 0xFF0 read only PrimeCell ID register a .
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