Fast Models Reference Manual - ARM Information Center

Processor Components
4.1 About the Code Translation processor components
This chapter provides an overview of the Programmer's View (PV) processor models of the
following ARM processors in Fast Models:
• Cortex-A15
• Cortex-A9
• Cortex-A8
• Cortex-A5
• Cortex-R5
• Cortex-R4
• Cortex-M4
• Cortex-M3
• ARMv7A - AEM
• ARM1176JZF-S
• ARM1136JF-S
• ARM968E-S
• ARM926EJ-S .
For details of the functionality of the hardware that the models simulate, see the relevant
processor technical reference manual.
PV models of processors and devices work at a level where functional behavior matches what
can be observed from software. Accuracy in timing is sacrificed to achieve fast simulation
speeds.
PV models translate ARM instructions on the fly and cache the translation to enable fast
execution of ARM code. They also use efficient PV bus models to enable fast access to memory
and devices.
The PV models implement most of the processor features but differ in certain key ways to allow
the models to run faster:
• timing is approximate
• caches, including smartcache, are implemented in selected processor models, although
cache control registers are implemented in all processor models
• write buffers are not implemented
• micro-architectural features, such as MicroTLB or branch cache, are not implemented
• by default, device-accurate modeling of multiple TLBs is turned off to improve
simulation performance
• the model uses a simplified view of the external buses
• except for the Cortex-A9 and Cortex-A5 processors, there is a single memory access port
combining instruction, data, DMA and peripheral access
• the Cortex-A9 model has three memory access ports, but only one is used
• for cores that support Jazelle, only trivial implementations are implemented
• the Cortex-A15 processor and the ARMv7A - Architecture Envelope Model (AEM) have
full CP14 implementation.
Performance counters are only partially implemented and only on certain processors.
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