Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Figure 5-42 PL340_DMC in System Canvas This component is written in LISA+. Ports Table 5-71 provides a brief description of the ports for the PL340_DMC component. Refer to the component documentation for more details. See the ARM PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual. Name Port protocol Type Description Table 5-71 PL340_DMC ports axi_chip_if_in[4] PVBus Slave Slave bus for connecting to bus decoder apb_interface PVBus Slave Slave bus interface for register access axi_chip_if_out[4] PVBus Master Master to connect to DRAM Additional protocols The PL340_DMC component has no additional protocols. Parameters Table 5-72 provides a description of the configuration parameters for the PL340_DMC component. Table 5-72 PL340_DMC configuration parameters Parameter name Description Type Allowed value Default value MEMORY_WIDTH Indicates the width, in bits, of connected memory Integer 16, 32, 64 32 IF_CHIP_0 to IF_CHIP_3 Indicates whether memory is connected Integer -1, 0 a -1 a. The allowed values have the following meanings: -1 nothing connected to the interface 0 DRAM connected. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-93 ID051811 Non-Confidential
Peripheral and Interface Components Registers Table 5-73 provides a description of the configuration registers for the PL340_DMC component. These are accessible through the APB interface. Table 5-73 PL340_DMC registers Register name Offset Access Description memc_status 0x000 read only Memory controller status register memc_cmd 0x004 write only Used to modify the state machine of the controller direct_cmd 0x008 write only Used to set the memory controller configurations memory_cfg 0x00C read/write Set/read the configuration of the controller refresh_prd 0x010 read/write Refresh period register cas_latency 0x014 read/write CAS latency register t_dqss 0x018 read/write t_dqss register t_mrd 0x01C read/write t_mrd register t_ras 0x020 read/write t_ras register t_rc 0x024 read/write t_rc register t_rcd 0x028 read/write t_rcd register t_rfc 0x02C read/write t_rfc register t_rp 0x030 read/write t_rp register t_rrd 0x034 read/write t_rrd register t_wr 0x038 read/write t_wr register t_wtr 0x03C read/write t_wtr register t_xp 0x040 read/write t_xp register t_xsr 0x044 read/write t_xsr register t_esr 0x048 read/write t_esr register id_00_cfg 0x100 read/write Sets the QOS id_01_cfg 0x104 read/write Sets the QOS id_02_cfg 0x108 read/write Sets the QOS id_03_cfg 0x10C read/write Sets the QOS id_04_cfg 0x110 read/write Sets the QOS id_05_cfg 0x114 read/write Sets the QOS id_06_cfg 0x118 read/write Sets the QOS id_07_cfg 0x11C read/write Sets the QOS ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-94 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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