Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components You must run this script from the directory in which it is installed, because it will not work correctly if run from any other location. Warning There is a temporary loss of network connectivity and your IP address might change. The uninstall script removes everything that can be safely removed. It does not remove: • symlinks to the init script • /sbin/brctl You must remove any symlinks that you have created. Removing brctl is optional. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-163 ID051811 Non-Confidential
Peripheral and Interface Components 5.7 CADI sync watchpoints Watchpoints are only supported by the CADI/Synchronous CADI (SCADI) interfaces of processor components. They are not supported by memory components like RAMDevice. When the simulator hits a watchpoint, the CADI/SCADI interface emits a sequence, typically just one, of modeChange(CADI_EXECMODE_Bpt, bptNumber) callbacks, where bptNumber is the breakpoint ID of the watchpoint. After this sequence it sends a modeChange(CADI_EXECMODE_Stop) callback. Only after the debugger receives this Stop callback might it inspect the state of the model. Additional information about the last of the hit watchpoints can be read from the following (non-architectural) core CADI registers in register group Simulation: memoryBptPC The PC of the instruction that caused the watchpoint to hit. memoryBptAccessVA Virtual address of the access or sub-access that caused the watchpoint to hit. memoryBptAccessSize Size in bytes of the access or sub-access that caused the watchpoint to hit. memoryBptAccessRW Type of access or sub-access that caused the watchpoint to hit: 1=read, 2=write, 3=both, 0=no access. These registers are not memory (or CPnn-) mapped anywhere and are not accessible to target programs. These registers are read-only. All registers are 32-bit. When multiple accesses have hit watchpoints at the same time, for example during the same instruction, the information contained in these registers is valid and consistent only for one of these accesses. Whenever at least one CADI watchpoint is set on a core, the syncLevel on that core is at least 2. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-164 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Emulation Baseboard Model: Platform
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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