Fast Models Reference Manual - ARM Information Center

Processor Components
All entries in the TLB are shown, regardless of security state or ASID. Entries outside the
current state, or that do not match the current ASID, are not be used by the CPU for physical
address translations.
This view is available only for TLBs with a limited, finite size. It is not supported when the
tlb_prefetch option is enabled, because there is no linear indexing of TLB entries in the infinite
pre-fetching TLB model.
Entries by MVA
The Address field corresponds to the Modified Virtual Address (MVA) from which a TLB entry
is translated.
This view is specific to a particular security state and ASID. You can control this by opening a
Register view in the debugger window. You can change the registers NS and ASID to view the
corresponding TLB entries.
4.12.7 Verification and Testing
The ARMAEMv7AMPCT has been tested using the ARM Architecture Verification Suite
(AVS).
4.12.8 Performance
The ARMAEMv7AMPCT model provides high performance in all areas except VFP and
NEON instruction set execution which currently does not use code translation technology.
4.12.9 Library dependencies
The ARMAEMv7AMPCT model has no dependencies on external libraries.
4.12.10 Boundary features and architectural checkers
Boundary features and architectural checkers are model capabilities that help your development
and testing process by exposing latent problems in the target code. For more information on
these capabilities, see Appendix A AEM ARMv7-A specifics.
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