Fast Models Reference Manual - ARM Information Center

Processor Components
Table 4-26 ARMCortexM3CT parameters (continued)
Parameter Description Type
Allowed
value
Default
value
semihosting-heap_base Virtual address of heap base. integer 0x00000000 -
0xFFFFFFFF
semihosting-heap_limit Virtual address of top of heap. integer 0x00000000 -
0xFFFFFFFF
0x0
0x10700000
semihosting-stack_base
Virtual address of base of
descending stack.
integer 0x00000000 -
0xFFFFFFFF
0x10700000
semihosting-stack_limit Virtual address of stack limit. integer 0x00000000 -
0xFFFFFFFF
0x10800000
a. The value of argv[0] points to the first command line argument, not to the name of an image.
4.11.4 Registers
The ARMCortexM3CT component provides the registers specified by the technical reference
manual for the Cortex-M3. Exceptions are listed in the section Differences between the CT
model and RTL implementations on page 4-58.
4.11.5 Caches
The ARMCortexM3CT component does not implement any caches.
4.11.6 Debug features
The ARMCortexM3CT component exports a CADI debug interface.
Registers
All processor and implemented registers are visible in the debugger. See the processor technical
reference manual for a detailed description of available registers.
Breakpoints
There is direct support for:
• single address unconditional instruction breakpoints
• unconditional instruction address range breakpoints
• single address unconditional data breakpoints.
The debugger might augment these with more complex combinations of breakpoints.
Memory
The ARMCortexM3CT component presents one 4GB view of virtual memory.
4.11.7 Verification and testing
The ARMCortexM3CT component has been tested using:
• the architecture validation suite tests for the ARM Cortex-M3
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