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Fast Models Reference Manual - ARM Information Center

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Accuracy and Functionality<br />

2.1 Model Capabilities Overview<br />

<strong>Fast</strong> <strong>Models</strong> attempt to accurately model the hardware, but compromises exist between speed<br />

of execution, accuracy and other criteria. This means that a processor model may not be<br />

expected to match the hardware under certain conditions.<br />

For a detailed description of timing, bus and cache modelling limitations see Functional caches<br />

in <strong>Fast</strong> <strong>Models</strong> on page 2-3 and How Accurate are <strong>Fast</strong> <strong>Models</strong>? on page 2-5.<br />

2.1.1 What <strong>Fast</strong> <strong>Models</strong> can do<br />

<strong>Fast</strong> <strong>Models</strong> do:<br />

• Instruction accurate modelling<br />

• Correct execution of well-written 1 code.<br />

2.1.2 What <strong>Fast</strong> <strong>Models</strong> cannot do<br />

<strong>Fast</strong> <strong>Models</strong> cannot be used to:<br />

• Validate the hardware<br />

• Model unpredictable behavior<br />

• Model cycle counting<br />

• Model timing sensitive behavior<br />

• Model SMP instruction scheduling<br />

• Model software performance<br />

• Model bus traffic.<br />

1. Well-written means “In accordance with the <strong>ARM</strong> Architecture <strong>Reference</strong> <strong>Manual</strong>s and the<br />

processor Technical <strong>Reference</strong> <strong>Manual</strong>”.<br />

<strong>ARM</strong> DUI 0423J Copyright © 2008-2011 <strong>ARM</strong>. All rights reserved. 2-2<br />

ID051811<br />

Non-Confidential

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