Fast Models Reference Manual - ARM Information Center

Processor Components
• booting of uClinux and RTX on an example system containing an ARMCortexM3CT
component.
4.11.8 Performance
The ARMCortexM3CT component provides high performance in all areas except with
instructions in protection regions smaller than 1KB.
4.11.9 Library dependencies
The ARMCortexM3CT component has no dependencies on external libraries.
4.11.10 Differences between the CT model and RTL implementations
The ARMCortexM3CT component differs from the corresponding revision of the ARM
Cortex-M3 RTL implementation in the following ways:
• The WIC is not currently implemented.
• Power control is not implemented, so the processor does not set the SLEEPING or
SLEEPDEEP signals. It does not support powering down of the processor.
• Only the minimal level of debug support is provided (no DAP, FPB, DWT or halting
debug capability).
• Debug-related components are not implemented. Processor debug registers and system
debug registers are not implemented.
• Debug interface port registers are not implemented.
• TPIU registers are not implemented.
• ETM registers are not implemented.
• The processor must still be clocked even if it has asserted the sleeping or sleepdeep
signals.
• Disabling processor features via the Auxiliary Control Register is not supported.
• Only a single pvbus_m master port is provided. This combines the ICode, DCode and
System bus interfaces of the RTL. The external PPB bus is provided by the pv_ppbus_m
master port.
• In privileged mode, STRT and LDRT to the PPB region are not forbidden access.
• No trace support (no ETM, ITM, TPUI or HTM).
• There is no supported equivalent of the RESET_ALL_REGS configuration setting in RTL
(that forces all registers to have a well defined value on reset).
• The RTL implements the ROM table as an external component on the External Private
Peripheral Bus. In the CT model the ROM table is implemented internally as a fallback if
an external PPB access in the ROM table address region aborts. This allows the default
ROM table to be overridden (by implementing an external component connected to the
external PPB to handle accesses to these addresses) without requiring every user of the
processor to implement and connect a ROM table component.
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